公开(公告)号：US10410916B2

公开(公告)日：2019-09-10

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Jiseok Hong ,  Kiseok Lee ,  Jemin Park ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

公开(公告)号：US20190088739A1

公开(公告)日：2019-03-21

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.

公开(公告)号：US20250151259A1

公开(公告)日：2025-05-08

申请号：US18657885

申请日：2024-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongjun Lee ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B12/00 ,  G11C11/16 ,  G11C11/4091

Abstract: Provided is a semiconductor device including a first word line extending in a first direction, bit lines extending in a second direction different from the first direction in a plan view, a second word line between ones of the bit lines and extending in the second direction, and a first memory cell. The first memory cell may include a first transistor electrically connected to a first one of the bit lines and the first word line, a second transistor electrically connected to the second word line and including source/drain electrodes, and a capacitor electrically connected to the second transistor. One of the source/drain electrodes of the second transistor may be electrically connected to the first transistor.

公开(公告)号：US20250071969A1

公开(公告)日：2025-02-27

申请号：US18623816

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Choi ,  Seungmuk Kim ,  Inwoo Kim ,  Sohyun Park ,  Hanseong Shin ,  Kiseok Lee ,  Hyunjin Lee ,  Hosang Lee ,  Hongjun Lee ,  Heejae Chae

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.

公开(公告)号：US20240404947A1

公开(公告)日：2024-12-05

申请号：US18673201

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Hanjin Lim ,  Jinwoo Han

IPC: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes: cell transistors stacked in a first direction perpendicular to an upper surface of a base, wherein each cell transistor includes a first source/drain region, a second source/drain region, and a gate electrode, a bit line extending in the first direction and electrically connected to the first source/drain regions; and data storage structures electrically connected to the second source/drain regions, wherein each gate electrode has a line shape extending in a second direction parallel to the upper surface, each data storage structure includes a first electrode, a second electrode, and a dielectric layer between the first and second electrodes, wherein the first electrodes are electrically connected to the second source/drain regions, wherein the second electrodes are stacked and spaced apart from each other in the first direction, and wherein each second electrode includes a line portion having a line shape extending in the second direction.

公开(公告)号：US20240357801A1

公开(公告)日：2024-10-24

申请号：US18530342

申请日：2023-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjin Lim ,  Jinwoo Han ,  Kiseok Lee ,  Keunnam Kim ,  Seokhan Park ,  Moonyoung Jeong

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/51

CPC classification number: H10B12/482 ,  H01L29/40111 ,  H01L29/516 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line extending in a first direction, an active pattern on the bit line, the active pattern including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction crossing the first direction, a gate insulating pattern between the first and second word lines and the active pattern, and a capacitor connected to each of the first and second vertical portions, the capacitor including a first electrode pattern connected to one of the first and second vertical portions, a second electrode pattern on the first electrode pattern, and a ferroelectric pattern between the first electrode pattern and the second electrode pattern.

公开(公告)号：US12075611B2

公开(公告)日：2024-08-27

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Min Tae Ryu ,  Woo Bin Song ,  Kiseok Lee ,  Minsu Lee ,  Min Hee Cho

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0607 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US12015064B2

公开(公告)日：2024-06-18

申请号：US17683765

申请日：2022-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin Lee ,  Kiseok Lee

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/423 ,  H01L29/402

Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

公开(公告)号：US11980025B2

公开(公告)日：2024-05-07

申请号：US17705991

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok Ahn ,  Huijung Kim ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

公开(公告)号：US11917815B2

公开(公告)日：2024-02-27

申请号：US18123736

申请日：2023-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L27/108 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/5283 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.