公开(公告)号：US20240170552A1

公开(公告)日：2024-05-23

申请号：US18215254

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbin Chun ,  Jinbum Kim ,  Gyeom Kim ,  Dahye Kim ,  Youngkwang Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including channels spaced apart from each other on a substrate; a gate structure extending on the substrate, the gate structure surrounding lower and upper surfaces and sidewalls of each of the channels; and a source/drain layer on the substrate, the source/drain layer contacting sidewalls of the channels and containing silicon-germanium, the source/drain layer including: a second epitaxial layer having a second germanium concentration; and a first epitaxial layer having a first germanium concentration smaller than the second germanium concentration, the first epitaxial layer covering a lower surface and sidewalls of the second epitaxial layer, wherein the first epitaxial layer includes a protruding portion that protrudes in the first direction and contacts the gate structure, and wherein the protruding portion has a facet that is not curved.

公开(公告)号：US11869765B2

公开(公告)日：2024-01-09

申请号：US17853990

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  Jinbum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L23/532 ,  B82Y10/00 ,  H01L29/10 ,  H01L29/161 ,  H01L21/28

CPC classification number: H01L21/02293 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US20230317792A1

公开(公告)日：2023-10-05

申请号：US18073806

申请日：2022-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dahye Kim ,  Kyungbin Chun

IPC: H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.

公开(公告)号：US11710796B2

公开(公告)日：2023-07-25

申请号：US17396059

申请日：2021-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Dongchan Suh ,  Jinbum Kim

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7854

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US11682673B2

公开(公告)日：2023-06-20

申请号：US17231502

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Jinbum Kim ,  Haejun Yu ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

公开(公告)号：US20230065755A1

公开(公告)日：2023-03-02

申请号：US17709940

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmoon Lee ,  Jinbum Kim ,  Dongsuk Shin

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/15

Abstract: A semiconductor device includes: an active region extending on a substrate in a first direction; a gate structure intersecting the active region and extending on the substrate in a second direction; and a source/drain region on the active region on at least one side of the gate structure. The source/drain region may include a first epitaxial layer on the active region and including impurities of a first conductivity type in a first concentration, a second epitaxial layer on the first epitaxial layer and including the impurities of the first conductivity type in a second concentration, and a first barrier layer between the first epitaxial layer and the second epitaxial layer, wherein the first barrier layer includes doped oxygen.

公开(公告)号：US20230051602A1

公开(公告)日：2023-02-16

申请号：US17725180

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Hyojin Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwon Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

公开(公告)号：US20220254878A1

公开(公告)日：2022-08-11

申请号：US17729676

申请日：2022-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US11362182B2

公开(公告)日：2022-06-14

申请号：US17088011

申请日：2020-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US11205649B2

公开(公告)日：2021-12-21

申请号：US16946060

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.