公开(公告)号：US12283497B2

公开(公告)日：2025-04-22

申请号：US17155672

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Uk Choi ,  Yeon Tae Kim ,  Tae Soon Park ,  Kee Soo Park ,  Sung-Gyu Park ,  Kwang-Hyun Yang ,  Seung Hun Lee

IPC: C23C16/52 ,  C23C16/44 ,  C23C16/455 ,  C30B25/08 ,  C30B25/10 ,  C30B25/16 ,  H01L21/67

Abstract: The present disclosure provides a semiconductor deposition monitoring device comprising a supporting table, a chamber, a lamp, an optical sensor, a conduit, a plurality of sensors in the conduit, and a heat exchanger. The supporting table supports a deposition target wafer on which a deposition material is deposited. The chamber comprises an upper dome and a lower dome. The lamp emits light to the chamber. The optical sensor receives the irradiated light and measures the deposition material formed in the chamber. The conduit has an inlet conduit through which air is injected into the chamber and an outlet conduit through which the air is discharged from the chamber. The plurality of sensors sense information of the air. The sensed information may be used to control the heat exchanger.

公开(公告)号：US12278271B2

公开(公告)日：2025-04-15

申请号：US17514379

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Jinbum Kim ,  Jaemun Kim ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/165 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a peripheral region, a first active pattern on the peripheral region, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns, which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, a first capping layer on the first active pattern, a second capping layer on the first capping layer, and a first gate insulating layer between the second capping layer and the first gate electrode. The first capping layer is between a sidewall of the first active pattern and the second capping layer. A concentration of germanium (Ge) of the first capping layer is greater than a concentration of germanium of the second capping layer.

公开(公告)号：US20250120149A1

公开(公告)日：2025-04-10

申请号：US18949790

申请日：2024-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/815 ,  H10D30/62 ,  H10D62/17

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US12206026B2

公开(公告)日：2025-01-21

申请号：US18207274

申请日：2023-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US12166081B2

公开(公告)日：2024-12-10

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US12159911B2

公开(公告)日：2024-12-03

申请号：US17552446

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Dongwoo Kim ,  Dongsuk Shin ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/41 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

公开(公告)号：US11935943B2

公开(公告)日：2024-03-19

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan Yu ,  Seung Hun Lee ,  Yang Xu

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/20 ,  H01L29/201 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US11888028B2

公开(公告)日：2024-01-30

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11777001B2

公开(公告)日：2023-10-03

申请号：US17742985

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US11705520B2

公开(公告)日：2023-07-18

申请号：US17657761

申请日：2022-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Jin Kim ,  Dong Woo Kim ,  Sang Moon Lee ,  Seung Hun Lee

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76829 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/0653

Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.