公开(公告)号：US09542977B2

公开(公告)日：2017-01-10

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka ,  Yuto Yakubo

IPC: G11C5/02 ,  H01L29/24 ,  H01L27/12 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US09240244B2

公开(公告)日：2016-01-19

申请号：US14200430

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/04 ,  G11C16/24 ,  G11C11/56 ,  G11C16/08 ,  H01L27/115 ,  H01L29/786 ,  H01L27/12

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US09092042B2

公开(公告)日：2015-07-28

申请号：US13908121

申请日：2013-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Koichiro Kamata ,  Tsutomu Murakawa ,  Takahiro Tsuji ,  Kaori Ikada

IPC: G05F3/16 ,  G05F1/00 ,  G05F1/56 ,  G05F3/24

CPC classification number: G05F3/16 ,  G05F1/56 ,  G05F3/242

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract translation: 本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。 在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器 在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。

公开(公告)号：US09076679B2

公开(公告)日：2015-07-07

申请号：US13900581

申请日：2013-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L29/788 ,  H01L27/108 ,  H01L27/115 ,  G11C16/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/11 ,  H01L49/02

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

公开(公告)号：US20150155289A1

公开(公告)日：2015-06-04

申请号：US14552551

申请日：2014-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: H01L27/115 ,  G11C16/24 ,  G11C16/08 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US08988116B2

公开(公告)日：2015-03-24

申请号：US13721120

申请日：2012-12-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Tatsuya Onuki

IPC: H03K3/00 ,  H03K17/06 ,  G11C11/403

CPC classification number: H03K17/063 ,  G11C11/403 ,  G11C2211/4016

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level

Abstract translation: 提供一种用于驱动半导体器件的方法，其允许减小电路的规模，降低功耗，并且提高读取数据的速度。 将H电平（数据“1”）电位或L电平（数据“0”）电位写入存储单元的节点。 源极线和位线的电位在M电平（L电平

公开(公告)号：US20140355339A1

公开(公告)日：2014-12-04

申请号：US14288894

申请日：2014-05-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Takanori Matsuzaki ,  Tomoaki Atsumi

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C11/403 ,  G11C11/4076 ,  G11C11/4094

Abstract: In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV

Abstract translation: 在包括第一至第三晶体管的存储单元中，当通过第一晶体管写入数据时，位线的电位被设置为VDD或GND。 在待机期间，位线的电位设置为GND。 在读取操作中，位线处于GND处的浮置状态，源极线被设置为电位VDD-α，因此第三晶体管导通。 然后，根据第二晶体管的栅极的电位输出源极线的电位。 注意，设置α，使得即使在待机期间第二晶体管的栅极的电位从VDD降低了＆Dgr; V，第二晶体管也可靠地关断。 也就是说，Vth +＆Dgr; V <α，其中Vth是第二晶体管的阈值。

公开(公告)号：US20140269099A1

公开(公告)日：2014-09-18

申请号：US14200430

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US20140266379A1

公开(公告)日：2014-09-18

申请号：US14199584

申请日：2014-03-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kei Takahashi ,  Tatsuya Onuki

IPC: H03K5/003

CPC classification number: H03K5/2481 ,  G11C27/024 ,  G11C27/026 ,  H03K5/249

Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.

Abstract translation: 包括晶体管和电容器的采样保持电路连接到差分电路。 采样保持电路通过采样操作对电容器进行充电或放电来获取用于校正差分电路的偏移电压的电压。 然后，它通过保持操作保持电容器的电位。 在差分电路的正常工作中，差分电路的输出电位由电容器保持的电位进行校正。 采样保持电路中的晶体管优选地是使用氧化物半导体形成沟道的晶体管。 氧化物半导体晶体管具有极低的漏电流; 因此，可以使采样保持电路的电容器中保持的电位变化最小化。

公开(公告)号：US20140264521A1

公开(公告)日：2014-09-18

申请号：US14287285

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: H01L27/105

CPC classification number: H01L27/1052 ,  G11C8/08 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4085 ,  G11C16/02 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/4016

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract translation: 即使在不提供电力的情况下也可以保存存储的数据，并且没有限制写入操作的数量的半导体装置。 使用可以充分降低诸如作为宽间隙半导体的氧化物半导体材料的晶体管的截止电流的材料形成半导体器件。 当使用可以充分降低晶体管的截止电流的半导体材料时，半导体器件可以长期保存数据。 此外，通过提供电连接到写字线的电容器或噪声去除电路，可以减少或去除诸如短脉冲或输入到存储器单元的噪声的信号。 因此，可以防止当存储单元中的晶体管瞬间导通时擦除写入存储单元的数据的故障。