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85 条记录 (耗时 0.026 秒)

    Semiconductor device and operating method of semiconductor device
    63.
    发明授权
    Semiconductor device and operating method of semiconductor device 有权

    公开(公告)号：US12034322B2

    公开(公告)日：2024-07-09

    申请号：US17422314

    申请日：2020-01-14

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yuki Okamoto ,  Takahiko Ishizu ,  Kei Takahashi ,  Takayuki Ikeda

    IPC分类号： H02J7/00 ,  H01M10/48

    CPC分类号： H02J7/0019 ,  H01M10/48 ,  H02J7/0016

    摘要： A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor. The semiconductor device has functions of supplying a ground potential to the other electrode of the capacitor; turning on the transistor; supplying a first potential to the one electrode of the capacitor; turning off the transistor; electrically connecting the other electrode of the capacitor and a negative electrode of the secondary battery corresponding to each cell balancing circuit; supplying a sum of the first potential and a potential of the negative electrode of the secondary battery corresponding to each cell balancing circuit, to the one electrode of the capacitor; and controlling charging of the secondary battery corresponding to each cell balancing circuit.

    Neural network circuit
    66.
    发明授权
    Neural network circuit 有权

    公开(公告)号：US11568223B2

    公开(公告)日：2023-01-31

    申请号：US16604363

    申请日：2018-04-02

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yuki Okamoto ,  Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda

    IPC分类号： G06F7/50 ,  G06F7/523 ,  G06F7/57 ,  G06F7/544 ,  G06N3/063

    摘要： A neural network circuit having a novel structure is provided.
    A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

    Memory device and method of operating the same
    67.
    发明授权
    Memory device and method of operating the same 有权

    公开(公告)号：US11423975B2

    公开(公告)日：2022-08-23

    申请号：US16968922

    申请日：2019-02-13

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Yuki Okamoto ,  Tatsuya Onuki

    IPC分类号： G11C11/4097 ,  G11C11/4091 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

    摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

    Single-polarity level shifter circuit and semiconductor device
    68.
    发明授权
    Single-polarity level shifter circuit and semiconductor device 有权

    公开(公告)号：US11296701B2

    公开(公告)日：2022-04-05

    申请号：US17286094

    申请日：2019-10-16

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Kei Takahashi ,  Yuki Okamoto ,  Takahiko Ishizu ,  Minato Ito

    IPC分类号： H03K19/018 ,  H03K19/0185

    摘要： A semiconductor device capable of level shifting in a negative potential direction using an n-channel transistor is provided. The semiconductor device includes a first source follower, a second source follower, and a comparator. The first source follower is supplied with a second high power supply potential and a low power supply potential; the second source follower is supplied with a first high power supply potential and the low power supply potential; and a digital signal which expresses a high level or a low level using the second high power supply potential or the first high power supply potential is input to the first source follower. Here, the second high power supply potential is a potential higher than the first high power supply potential, and the first high power supply potential is a potential higher than the low power supply potential. The comparator compares output potentials of the first source follower and the second source follower and outputs a digital signal which expresses a high level or a low level using the first high power supply potential or the low power supply potential.

    Memory device
    69.
    发明授权
    Memory device 有权

    公开(公告)号：US11270997B2

    公开(公告)日：2022-03-08

    申请号：US16757025

    申请日：2018-11-19

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Tatsuya Onuki ,  Yuki Okamoto ,  Hisao Ikeda ,  Shuhei Nagatsuka

    IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

    摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

    Display controller, display system, and electronic device
    70.
    发明授权
    Display controller, display system, and electronic device 有权

    公开(公告)号：US11217173B2

    公开(公告)日：2022-01-04

    申请号：US16690814

    申请日：2019-11-21

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yuki Okamoto

    IPC分类号： G09G3/3258 ,  G09G3/3233 ,  G09G3/36 ,  G09G3/20 ,  H01L21/02 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1368 ,  H01L27/32 ,  G06F3/041 ,  G09G3/3225 ,  H01L29/786 ,  H01L27/12

    摘要： A display system includes a host device, a display controller, and a display panel. The display panel includes a pixel array including a plurality of subpixels each including a light-emitting display element and a reflective display element. The host device sends image data DT0 to the display controller. The display controller has the following functions: color classification of the image data DT0; generation of attribute data based on the classification result; generation of image data DT1 from the image data DT0; generation of two kinds of image data DT2_e and DT2_r through image processing of the image data DT1 in accordance with the attribute data; generation of image data DT3_e from the image data DT2_e; and generation of image data DT3_r from the image data DT2_r. The image data DT3_e is displayed by the light-emitting display element, and the image data DT3_r is displayed by the reflective display element.