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公开(公告)号：US20120326244A1
公开(公告)日：2012-12-27
申请号：US13554204
申请日：2012-07-20
CPC分类号： H01L29/785 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/02266 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L28/40 , H01L29/517 , H01L29/7833 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate with being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.
摘要翻译： 半导体器件包括半导体衬底，源极区，漏极区，绝缘膜和栅电极。 源区域形成在半导体衬底中。 漏区形成在半导体衬底中，与源极区分开。 绝缘膜形成在源极区域和漏极区域之间并且在半导体衬底上或上方。 绝缘膜包括含有选自Si，Ge，Mg，Ca，Sr，Ba和N中的至少一种元素的铝酸镧铝。铝酸镧含有选自Ti，Hf和Zr中的至少一种元素。 栅电极形成在绝缘膜上。
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62.发明申请公开(公告)号：US20120068254A1
公开(公告)日：2012-03-22
申请号：US13072366
申请日：2011-03-25
申请人： Kiwamu SAKUMA , Atsuhiro Kinoshita
发明人： Kiwamu SAKUMA , Atsuhiro Kinoshita
IPC分类号： H01L29/792 , H01L21/308
CPC分类号： H01L29/792 , H01L27/11524 , H01L27/11551 , H01L29/7881
摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.
摘要翻译： 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。
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公开(公告)号：US07690024B2
公开(公告)日：2010-03-30
申请号：US11350075
申请日：2006-02-09
CPC分类号： H04L63/0853 , H04L63/1441 , H04W12/06 , H04W12/12
摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.
摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。
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64.发明授权公开(公告)号：US07569879B2
公开(公告)日：2009-08-04
申请号：US11699334
申请日：2007-01-30
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译： 非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域 在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电 通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域 位置高 她比第三个导电区域。
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公开(公告)号：US20090083202A1
公开(公告)日：2009-03-26
申请号：US12211739
申请日：2008-09-16
申请人： CHIKA TANAKA , Atsuhiro Kinoshita
发明人： CHIKA TANAKA , Atsuhiro Kinoshita
CPC分类号： G06N3/063 , G11C16/22 , G11C27/005
摘要： A semiconductor storage device includes a storage part including a plurality of nonvolatile semiconductor memory cells each having a conductive path, a charge storage layer and a control gate electrode. The device further includes a plurality of first input terminals each connected to one end of the conductive path of each nonvolatile semiconductor memory cell, a plurality of second input terminals each connected to the control gate of each nonvolatile semiconductor memory cell, and an output end connected to the other ends of the conductive paths of the plurality of nonvolatile semiconductor memory cells, respectively.
摘要翻译： 一种半导体存储装置，包括具有导电路径的多个非易失性半导体存储单元，电荷存储层和控制栅电极的存储部。 该装置还包括多个第一输入端子，每个第一输入端子连接到每个非易失性半导体存储单元的导电路径的一端，多个第二输入端子，每个第二输入端子连接到每个非易失性半导体存储器单元的控制栅极，并且输出端连接 分别连接到多个非易失性半导体存储单元的导电路径的另一端。
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公开(公告)号：US20080179752A1
公开(公告)日：2008-07-31
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L29/78 , H01L21/336 , H01L23/48
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅极两侧的衬底表面中或其上形成一对重掺杂的p（p + SUP +）型扩散层，使其浓度达到5×10 19 原子/ cm 3以上且小于或等于1×10 21原子/ cm 3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p + + +层。
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公开(公告)号：US20070052031A1
公开(公告)日：2007-03-08
申请号：US11404075
申请日：2006-04-14
申请人： Atsuhiro Kinoshita
发明人： Atsuhiro Kinoshita
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L29/665 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage. A semiconductor device includes: a MOS transistor including a first gate insulating film provided on a first element region of first conductivity-type in a semiconductor, a first gate electrode provided on the first gate insulating film, and first impurity regions of second conductivity-type provided in the first element region on both sides of the first gate electrode; and an ESD protection element including a second gate insulating film provided on a second element region of first conductivity-type in the semiconductor substrate and having substantially the same thickness as the first gate insulating film, a second gate electrode provided on the second gate insulating film and connected to the first gate electrode, and second impurity regions of second conductivity-type provided in the second element region on both sides of the second gate electrode.
摘要翻译： 即使要被保护的半导体器件包括具有低介电击穿电压的栅极绝缘膜，也可以容易地设定保护电压。 半导体器件包括：MOS晶体管，包括设置在半导体中的第一导电类型的第一元件区域上的第一栅极绝缘膜，设置在第一栅极绝缘膜上的第一栅极电极和第二导电类型的第一杂质区域 设置在所述第一栅电极的两侧的所述第一元件区域中; 以及ESD保护元件，包括设置在半导体衬底中的第一导电类型的第二元件区上并具有与第一栅极绝缘膜基本相同的厚度的第二栅极绝缘膜，设置在第二栅极绝缘膜上的第二栅电极 并且连接到第一栅电极，以及设置在第二栅电极两侧的第二元件区中的第二导电类型的第二杂质区。
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公开(公告)号：US20060220131A1
公开(公告)日：2006-10-05
申请号：US11384269
申请日：2006-03-21
IPC分类号： H01L21/8234 , H01L27/12 , H01L21/336 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/78618
摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.
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公开(公告)号：US09530499B2
公开(公告)日：2016-12-27
申请号：US13557401
申请日：2012-07-25
CPC分类号： G11C15/04 , G06F17/30864 , G06F17/30949 , G06F17/30985 , G11C15/00
摘要： According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.
摘要翻译： 根据一个实施例，半导体存储器件包括存储器和控制器。 存储器存储包括条目的数据片段和搜索信息，其中每个条目与用于指定一个数据片段的搜索关键字和存储数据片段的实际地址相关联。 当接收到第一命令时，控制器在第一命令指定搜索关键字时，输出与包括搜索关键字的一个条目相对应的一个数据段，并且当第一命令指定一个实际地址时，输出与一个对应的一个数据 输入包括真实地址。
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公开(公告)号：US08849219B2
公开(公告)日：2014-09-30
申请号：US13599413
申请日：2012-08-30
申请人： Jun Deguchi , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
发明人： Jun Deguchi , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
CPC分类号： H03M1/66 , H03M1/1061 , H03M1/745
摘要： In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n−1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
摘要翻译： 通常，根据一个实施例，配置成将包括n（n> 1）位的数字信号转换为模拟电流以从输出端输出模拟电流的DA转换器包括n个电压 - 电流转换器。 它们中的每一个对应于数字信号的每个位，并且被配置为根据相应的位产生电流。 第k（k是0到n-1的整数）电压 - 电流转换器包括阈值电压可调的第一晶体管。 第一晶体管包括半导体衬底，第一扩散区，第二扩散区，绝缘膜，电荷累积膜和栅极。
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