公开(公告)号：US11798619B2

公开(公告)日：2023-10-24

申请号：US17857113

申请日：2022-07-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

公开(公告)号：US20230325650A1

公开(公告)日：2023-10-12

申请号：US17847491

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  MARK REITEN

IPC: G06G7/06 ,  G06G7/16

CPC classification number: G06G7/06 ,  G06G7/16

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; and an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising a neuron scalar to generate a scaled current from the received respective neuron current, and a current-to-voltage converter to convert the scaled current into the respective output voltage.

公开(公告)号：US11783904B2

公开(公告)日：2023-10-10

申请号：US17839294

申请日：2022-06-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

CPC classification number: G11C16/3459 ,  G06F3/0688 ,  G06N3/063 ,  G06N3/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/10

Abstract: In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

公开(公告)号：US20230259738A1

公开(公告)日：2023-08-17

申请号：US18141090

申请日：2023-04-28

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Hieu Van Tran ,  NHAN DO ,  FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

公开(公告)号：US11683933B2

公开(公告)日：2023-06-20

申请号：US17121555

申请日：2020-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC classification number: H01L27/11531 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

公开(公告)号：US20230119017A1

公开(公告)日：2023-04-20

申请号：US18081124

申请日：2022-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/065 ,  G11C16/10 ,  G11C16/04 ,  G06N3/08 ,  G06F12/0811 ,  G11C11/4063 ,  G11C11/54

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

公开(公告)号：US20230049032A1

公开(公告)日：2023-02-16

申请号：US17521772

申请日：2021-11-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu

IPC: G06N3/063 ,  G11C16/26

Abstract: Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In some embodiments, a common mode circuit is used with differential cells, W+ and W−, that together store a weight, W. The common mode circuit can utilize current sources, variable resistors, or transistors as part of the structure for introducing a common mode voltage bias.

公开(公告)号：US11538532B2

公开(公告)日：2022-12-27

申请号：US17199383

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  Chunming Wang ,  Nhan Do ,  Hieu Van Tran

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F11/14 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H03K19/20

Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

公开(公告)号：US20220254414A1

公开(公告)日：2022-08-11

申请号：US17734807

申请日：2022-05-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.

公开(公告)号：US11355184B2

公开(公告)日：2022-06-07

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.