公开(公告)号：US20080001173A1

公开(公告)日：2008-01-03

申请号：US11767188

申请日：2007-06-22

申请人： Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi ,  Yanning Sun

发明人： Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi ,  Yanning Sun

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/7787 ,  H01L29/66462

摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

公开(公告)号：US20070228484A1

公开(公告)日：2007-10-04

申请号：US11762376

申请日：2007-06-13

申请人： STEVEN KOESTER ,  Devendra Sadana ,  Ghavam Shahidi

发明人： STEVEN KOESTER ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L29/768 ,  H01L21/30

CPC分类号： H01L21/823807 ,  H01L21/02002 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203

摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

摘要翻译： 制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。 绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。 第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。 半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。 在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

公开(公告)号：US20070122634A1

公开(公告)日：2007-05-31

申请号：US11164345

申请日：2005-11-18

申请人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

发明人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

IPC分类号： B32B13/04 ,  B05D5/12

CPC分类号： H01L21/84 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/04

摘要： A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.

摘要翻译： 公开了一种用于半导体器件的衬底，在一个实施例中，包括在单个堆叠中彼此结合的多个绝缘体上半导体（SOI）晶片。 堆叠的远端包括具有厚度和第一表面取向的第一半导体层的第一SOI区域。 单个堆叠的表面可以进一步包括非SOI区域和/或至少一个第二SOI区域。 非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。 每个第二SOI区域具有与第一半导体层的厚度不同的第二半导体层和/或与第一表面取向不同的表面取向。 因此，衬底允许在可以包括不同表面取向和/或不同厚度和/或不同的体或SOI结构的最佳衬底区域上形成不同的器件。

公开(公告)号：US20060211184A1

公开(公告)日：2006-09-21

申请号：US11436756

申请日：2006-05-18

申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

IPC分类号： H01L21/84

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78684

摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

摘要翻译： 本发明提供一种具有低外部电阻的薄沟道MOSFET。 广义而言，包括位于掩埋绝缘层顶部的SOI层的绝缘体上硅结构，所述SOI层具有沟槽区，该沟道区被存在位于并接触之下的下面的局部氧化物区域 与所述掩埋绝缘层; 以及位于所述SOI层上方的栅极区域，其中所述局部氧化物区域与栅极区域自对准。 还提供了一种用于形成本发明的MOSFET的方法，包括在衬底顶部形成虚拟栅极区; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

公开(公告)号：US20060024931A1

公开(公告)日：2006-02-02

申请号：US10902557

申请日：2004-07-29

申请人： Kevin Chan ,  Joel de Souza ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

发明人： Kevin Chan ,  Joel de Souza ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/20 ,  H01L21/425 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

摘要： This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.

摘要翻译： 本发明提供了通过注入氧（SIMOX）分离方法，用于形成具有不同晶体取向的平面杂化取向绝缘体上半导体（SOI）衬底，从而使得可以以提供最佳性能的晶体取向来制造器件。 该方法包括以下步骤：从具有第二晶体取向的顶部半导体层选择具有由薄绝缘层分离的第一晶体取向的基底半导体层的衬底; 用具有第一晶体取向的外延生长的半导体代替选定区域中的顶部半导体层; 然后使用离子注入和退火方法来（i）在外延生长的半导体材料内形成掩埋绝缘区，并且（ii）加厚顶部半导体层下面的绝缘层，从而形成混合取向基板，其中两个半导体材料 具有不同的晶体取向具有基本上相同的厚度并且均设置在公共掩埋绝缘体层上。 在该方法的变型中，替代地使用离子注入和退火方法将辅助掩埋绝缘体层（最初在基底半导体层下面）向上（i）延伸到外延生长的半导体中，以及（ii）直到绝缘层 在顶部半导体层下面。

公开(公告)号：US20050118826A1

公开(公告)日：2005-06-02

申请号：US10725848

申请日：2003-12-02

申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/311 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/26533 ,  H01L21/28202 ,  H01L29/1083 ,  H01L29/49 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

摘要翻译： 本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。 具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。 提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

公开(公告)号：US20050006704A1

公开(公告)日：2005-01-13

申请号：US10900523

申请日：2004-07-28

申请人： Tak Ning ,  Devendra Sadana

发明人： Tak Ning ,  Devendra Sadana

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/02 ,  H01L27/12 ,  H01L29/06 ,  H01L31/072

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

摘要翻译： 本发明提供SOI材料，其包括具有不同厚度的区域的顶部含Si层以及制造这种SOI材料的方法。 本发明的方法包括通过硅的掩蔽氧化来稀释顶部含Si层的预定区域的步骤。 还公开了包括具有不同类型的CMOS器件的本发明SOI材料的SOI IC芯片。

公开(公告)号：US20050003626A1

公开(公告)日：2005-01-06

申请号：US10896812

申请日：2004-07-22

申请人： Stephen Fox ,  Neena Garg ,  Kenneth Giewont ,  Junedong Lee ,  Siegfried Maurer ,  Dan Moy ,  Maurice Norcott ,  Devendra Sadana

发明人： Stephen Fox ,  Neena Garg ,  Kenneth Giewont ,  Junedong Lee ,  Siegfried Maurer ,  Dan Moy ,  Maurice Norcott ,  Devendra Sadana

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/425

CPC分类号： H01L21/76243

摘要： A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

摘要翻译： 描述了一种用于形成绝缘体上半导体（SOI）衬底的方法，其包括加热衬底，将氧注入加热衬底，冷却衬底，注入冷却衬底和退火的步骤。 植入的步骤可以是几种能量以提供多个深度和相应的埋入损伤区域。 在植入之前，可以执行清洁衬底表面和/或在其上形成图案化掩模的步骤。 本发明克服了提高掩埋氧化物质量及其性能如表面粗糙度，均匀厚度和击穿电压Vbd的问题。

公开(公告)号：US08823127B2

公开(公告)日：2014-09-02

申请号：US13614953

申请日：2012-09-13

申请人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

IPC分类号： H01L31/06 ,  H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L31/068 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548

摘要： A multijunction photovoltaic (PV) cell includes a bottom flexible substrate and a bottom metal layer located on the bottom flexible substrate. The multijunction photovoltaic cell also includes a semiconductor layer located on the bottom metal layer and a stack having a plurality of junctions located on the semiconductor layer, each of the plurality of junctions having a respective bandgap. The pluralities of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack.

摘要翻译： 多结光伏（PV）电池包括底部柔性基底和位于底部柔性基底上的底部金属层。 所述多结光伏电池还包括位于所述底部金属层上的半导体层和具有位于所述半导体层上的多个结的叠层，所述多个结中的每一个具有相应的带隙。 多个接合点从具有位于衬底上的最小带隙的接合点排列到具有位于堆叠顶部的最大带隙的接合点。

公开(公告)号：US20120193687A1

公开(公告)日：2012-08-02

申请号：US13017127

申请日：2011-01-31

申请人： Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

发明人： Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/20 ,  H01L21/26513 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

摘要： Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.

摘要翻译： 本发明的实施例提供一种制造电接触的方法。 该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。 该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域， 通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上层金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层， 将无定形锗层转化为结晶锗层并激活注入的掺杂剂。 电接触可以是晶体管的源极或漏极接触。