公开(公告)号：US20200006547A1

公开(公告)日：2020-01-02

申请号：US16284871

申请日：2019-02-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

公开(公告)号：US10446669B2

公开(公告)日：2019-10-15

申请号：US15964398

申请日：2018-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Han Fan ,  Wei-Yuan Lu ,  Yu-Lin Yang ,  Chun-Hsiang Fan ,  Sai-Hooi Yeong

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311

摘要： A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.

公开(公告)号：US10325911B2

公开(公告)日：2019-06-18

申请号：US15696573

申请日：2017-09-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Yuan Lu ,  Sai-Hooi Yeong

IPC分类号： H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L21/768 ,  H01L29/49

摘要： In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

公开(公告)号：US20190148528A1

公开(公告)日：2019-05-16

申请号：US15962500

申请日：2018-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02

摘要： Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.

公开(公告)号：US10269697B2

公开(公告)日：2019-04-23

申请号：US15061627

申请日：2016-03-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Yen Liu ,  Boo Yeh ,  Min-Chang Liang ,  Jui-Yao Lai ,  Sai-Hooi Yeong ,  Ying-Yan Chen ,  Yen-Ming Chen

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

摘要： A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

公开(公告)号：US10103146B2

公开(公告)日：2018-10-16

申请号：US15838451

申请日：2017-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

摘要： A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US10062688B2

公开(公告)日：2018-08-28

申请号：US14987509

申请日：2016-01-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Tsung-Yao Wen ,  Yen-Ming Chen

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/265 ,  H01L21/223

CPC分类号： H01L27/0886 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first direction over a substrate and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and a first insulating gate sidewall on a first lateral surface of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate structure. A portion of the source/drain region extends under the insulating gate sidewall for a substantially constant distance along the first direction.

公开(公告)号：US20180175175A1

公开(公告)日：2018-06-21

申请号：US15653720

申请日：2017-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L21/265

CPC分类号： H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165

摘要： Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20180166442A1

公开(公告)日：2018-06-14

申请号：US15838451

申请日：2017-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC分类号： H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847

摘要： A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US09954076B2

公开(公告)日：2018-04-24

申请号：US15486549

申请日：2017-04-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Hao Yu ,  Sheng-chen Wang ,  Sai-Hooi Yeong

IPC分类号： H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.