公开(公告)号：US20140181165A1

公开(公告)日：2014-06-26

申请号：US14192102

申请日：2014-02-27

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示波纹部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

公开(公告)号：US20240354259A1

公开(公告)日：2024-10-24

申请号：US18732865

申请日：2024-06-04

Applicant: Texas Instruments Incorporated

Inventor： Asheesh Bhardwaj ,  Mujibur Rahman ,  Timothy David Anderson

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

公开(公告)号：US20240311313A1

公开(公告)日：2024-09-19

申请号：US18660120

申请日：2024-05-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.

公开(公告)号：US12045172B2

公开(公告)日：2024-07-23

申请号：US17987020

申请日：2022-11-15

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson

IPC: G06F7/487 ,  G06F7/24 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

公开(公告)号：US12032490B2

公开(公告)日：2024-07-09

申请号：US18073313

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F12/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

公开(公告)号：US20230333848A1

公开(公告)日：2023-10-19

申请号：US18320625

申请日：2023-05-19

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Asheesh Bhardwaj ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F17/16 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/38 ,  G06F7/57 ,  G06F9/48

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F17/16 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/24 ,  G06F9/30032 ,  H03H17/0664 ,  G06F7/53 ,  G06F9/3836 ,  G06F9/30021 ,  G06F7/487 ,  G06F9/3818 ,  G06F7/57 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3851 ,  G06F9/48

Abstract: A method includes executing, by a processor a vector finite impulse response (VFIR) filter instruction that specifies coefficients, data elements, and a storage location. The executing includes reordering a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of a vector multiplier of the processor, generating, by the vector multiplier, filter outputs based on the coefficients and data elements, and storing the filter outputs in the storage location.

公开(公告)号：US11609862B2

公开(公告)日：2023-03-21

申请号：US17665958

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F12/1045 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

Abstract: A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

公开(公告)号：US11500631B2

公开(公告)日：2022-11-15

申请号：US16878610

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F17/16 ,  G06F7/24 ,  H03H17/06 ,  G06F9/38

Abstract: A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

公开(公告)号：US11347503B2

公开(公告)日：2022-05-31

申请号：US16878607

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Asheesh Bhardwaj ,  Mujibur Rahman ,  Timothy David Anderson

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

公开(公告)号：US11294673B2

公开(公告)日：2022-04-05

申请号：US16878608

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.