公开(公告)号：US20200312747A1

公开(公告)日：2020-10-01

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US10748999B2

公开(公告)日：2020-08-18

申请号：US16229827

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808 ,  H01L29/66

Abstract: A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.

公开(公告)号：US20200251257A1

公开(公告)日：2020-08-06

申请号：US16854839

申请日：2020-04-21

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01B13/00 ,  H01L23/00 ,  H01B1/02

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

公开(公告)号：US10566267B2

公开(公告)日：2020-02-18

申请号：US15984343

申请日：2018-05-19

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532 ,  H01L23/00

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US10544034B1

公开(公告)日：2020-01-28

申请号：US16042595

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Kathryn Schuck

IPC: H01L23/52 ,  H01L29/40 ,  B81B7/00 ,  B81C1/00 ,  H01L23/00

Abstract: A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer.

公开(公告)号：US20200020656A1

公开(公告)日：2020-01-16

申请号：US16580973

申请日：2019-09-24

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Salvatore Frank Pavone ,  Christopher Daniel Manack

IPC: H01L23/00 ,  C25D5/12

Abstract: A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

公开(公告)号：US20200006134A1

公开(公告)日：2020-01-02

申请号：US16022956

申请日：2018-06-29

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US12180595B2

公开(公告)日：2024-12-31

申请号：US17683222

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand

IPC: H01L21/48 ,  C23C22/40 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: In examples, a method of forming a semiconductor package comprises forming a conversion coating solution comprising a salt of a vanadate, a salt of a zirconate, or both with a complexing agent; cleaning a copper lead frame, wherein the cleaned copper lead frame comprises copper oxide on an outer surface thereof; immersing the cleaned copper lead frame in the conversion coating solution; rinsing the copper lead frame; and forming an assembly by coupling a semiconductor die to the copper lead frame, coupling the semiconductor die to a lead of the copper lead frame, applying a mold compound onto at least a portion of the outer surface of the copper lead frame, and curing the mold compound. An adhesion strength at an interface between the mold compound and the at least the portion of the outer surface of the copper lead frame is increased relative to a same assembly formed without immersing the copper lead frame in the conversion coating solution.

公开(公告)号：US12074096B2

公开(公告)日：2024-08-27

申请号：US16793887

申请日：2020-02-18

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Pavone

IPC: H01L23/495 ,  H01L21/683 ,  H01L23/00 ,  H01L23/36 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532

CPC classification number: H01L23/49517 ,  H01L23/49 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US20240153841A1

公开(公告)日：2024-05-09

申请号：US18544590

申请日：2023-12-19

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/373 ,  H01L21/32051 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/53209

Abstract: In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.