公开(公告)号：US11837504B2

公开(公告)日：2023-12-05

申请号：US17195282

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7843 ,  H01L21/845 ,  H01L27/1211

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

公开(公告)号：US20230387124A1

公开(公告)日：2023-11-30

申请号：US18361704

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi Ning Ju ,  Jia-Chuan You ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823481

Abstract: A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

公开(公告)号：US20230386933A1

公开(公告)日：2023-11-30

申请号：US18447922

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L27/0924 ,  H01L29/7831 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L21/823468 ,  H01L29/7843 ,  H01L27/0886 ,  H01L29/41791 ,  H01L21/845 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

公开(公告)号：US11799019B2

公开(公告)日：2023-10-24

申请号：US17091767

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US11676864B2

公开(公告)日：2023-06-13

申请号：US17005172

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Shang-Wen Chang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

公开(公告)号：US11626509B2

公开(公告)日：2023-04-11

申请号：US17314763

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

公开(公告)号：US11616062B2

公开(公告)日：2023-03-28

申请号：US17170740

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Zhi-Chang Lin ,  Chih-Hao Wang ,  Shih-Cheng Chen

IPC: H01L29/423 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

公开(公告)号：US11569234B2

公开(公告)日：2023-01-31

申请号：US17027322

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Yi-Ruei Jhan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

公开(公告)号：US11563106B2

公开(公告)日：2023-01-24

申请号：US16858891

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/51

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

公开(公告)号：US11527533B2

公开(公告)日：2022-12-13

申请号：US16888457

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.