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公开(公告)号:US20220208680A1
公开(公告)日:2022-06-30
申请号:US17696910
申请日:2022-03-17
发明人: Po-Yuan Teng , Hung-Yi Kuo , Hao-Yi Tsai , Tin-Hao Kuo , Yu-Chia Lai , Shih-Wei Chen
IPC分类号: H01L23/538 , H01L23/31 , H01L23/473 , H01L21/56 , H01L21/48
摘要: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.
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62.
公开(公告)号:US20220077024A1
公开(公告)日:2022-03-10
申请号:US17525971
申请日:2021-11-15
发明人: Po-Yuan Teng , Chen-Hua Yu , Hao-Yi Tsai , Kuo-Chung Yee , Tin-Hao Kuo , Shih-Wei Chen
IPC分类号: H01L23/473 , H01L23/31 , H01L23/40 , H01L21/56 , H01L21/48 , H01L23/00 , H01L21/683
摘要: A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.
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公开(公告)号:US11004758B2
公开(公告)日:2021-05-11
申请号:US16442907
申请日:2019-06-17
发明人: Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Pei-Hsuan Lee , Chien Ling Hwang , Yu-Chia Lai , Po-Yuan Teng , Chen-Hua Yu
IPC分类号: H01L23/538 , H01L21/56 , H01L23/31 , H01L23/32 , H01L23/00 , H01L25/065
摘要: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
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公开(公告)号:US10985114B2
公开(公告)日:2021-04-20
申请号:US16661785
申请日:2019-10-23
发明人: Yu-Feng Chen , Yen-Liang Lin , Tin-Hao Kuo , Sheng-Yu Wu , Chen-Shien Chen
IPC分类号: H01L23/00 , H01L23/485 , H01L21/768 , H01L23/31
摘要: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
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公开(公告)号:US20210013177A1
公开(公告)日:2021-01-14
申请号:US17035730
申请日:2020-09-29
发明人: Shih-Wei Chen , Chih-Hua Chen , Hsin-Yu Pan , Hao-Yi Tsai , Lipu Kris Chuang , Tin-Hao Kuo
IPC分类号: H01L23/00 , H01L23/31 , H01L25/065 , H01L21/56 , H01L25/00 , H01L23/367 , H01L23/373 , H01L23/538
摘要: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.
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公开(公告)号:US20210005586A1
公开(公告)日:2021-01-07
申请号:US17023379
申请日:2020-09-17
发明人: Chi-Hui Lai , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Tin-Hao Kuo
摘要: A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
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公开(公告)号:US20200243429A1
公开(公告)日:2020-07-30
申请号:US16529119
申请日:2019-08-01
发明人: Chi-Hui Lai , Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号: H01L23/498 , H01L23/538 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/00
摘要: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
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公开(公告)号:US20200211922A1
公开(公告)日:2020-07-02
申请号:US16529023
申请日:2019-08-01
发明人: Shu-Rong Chun , Kuo Lung Pan , Pei-Hsuan Lee , Chien Ling Hwang , Yu-Chia Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chen-Hua Yu
摘要: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.
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公开(公告)号:US20190326236A1
公开(公告)日:2019-10-24
申请号:US16459083
申请日:2019-07-01
发明人: Chen-Hua Yu , Tin-Hao Kuo , Chung-Shi Liu , Hao-Yi Tsai
IPC分类号: H01L23/00
摘要: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.
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公开(公告)号:US20190252347A1
公开(公告)日:2019-08-15
申请号:US16390953
申请日:2019-04-22
发明人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo
IPC分类号: H01L23/00 , H01L23/498 , H05K3/34
CPC分类号: H01L24/81 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/10175 , H01L2224/13013 , H01L2224/13014 , H01L2224/13023 , H01L2224/131 , H01L2224/13147 , H01L2224/13294 , H01L2224/133 , H01L2224/16012 , H01L2224/16013 , H01L2224/16113 , H01L2224/16227 , H01L2224/16238 , H01L2224/8112 , H01L2224/81385 , H01L2224/81447 , H01L2224/81815 , H01L2924/12042 , H01L2924/14 , H01L2924/381 , H01L2924/3841 , H05K3/3436 , H05K2201/10674 , H05K2203/1173 , Y02P70/613 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要: A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
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