公开(公告)号：US11942442B2

公开(公告)日：2024-03-26

申请号：US17080826

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan

IPC: H01L23/66 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/0401

Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

公开(公告)号：US20240071888A1

公开(公告)日：2024-02-29

申请号：US17897206

申请日：2022-08-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chang Lin ,  Yen-Fu Su ,  Chin-Liang Chen ,  Wei-Yu Chen ,  Hsin-Yu Pan ,  Yu-Min Liang ,  Hao-Cheng Hou ,  Chi-Yang Yu

IPC: H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/0652 ,  H01L24/16

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate.

公开(公告)号：US20220359382A1

公开(公告)日：2022-11-10

申请号：US17870798

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Yi-Che Chiang

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/36 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

公开(公告)号：US20220238505A1

公开(公告)日：2022-07-28

申请号：US17721342

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/34 ,  H01L21/56

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

公开(公告)号：US20180323118A1

公开(公告)日：2018-11-08

申请号：US16019083

申请日：2018-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Ding Wang ,  An-Jhih Su ,  Chien Ling Hwang ,  Jung Wei Cheng ,  Hsin-Yu Pan ,  Chen-Hua Yu

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/42 ,  H01L21/56 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L23/04 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/023 ,  H01L2224/04026 ,  H01L2224/11616 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27602 ,  H01L2224/27616 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/29166 ,  H01L2224/29181 ,  H01L2224/29187 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29309 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/00012 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

公开(公告)号：US20170250130A1

公开(公告)日：2017-08-31

申请号：US15595531

申请日：2017-05-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/532

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US20160307852A1

公开(公告)日：2016-10-20

申请号：US14688862

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16104 ,  H01L2924/00014

Abstract: An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer.

Abstract translation: 实施例器件封装包括半导体器件裸片，其包括在顶表面处的钝化层，钝化层上方的电连接到器件裸片的第一导电线，以及钝化层上的第二导电线，并电连接到器件裸片 。 第一导电线比第二导线更厚，第一导线和第二导线形成在相同的器件封装层中。

公开(公告)号：US12230589B2

公开(公告)日：2025-02-18

申请号：US18325136

申请日：2023-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yang Yu ,  Jung-Wei Cheng ,  Yu-Min Liang ,  Jiun-Yi Wu ,  Yen-Fu Su ,  Chien-Chang Lin ,  Hsin-Yu Pan

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

公开(公告)号：US20240194619A1

公开(公告)日：2024-06-13

申请号：US18444742

申请日：2024-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan

IPC: H01L23/66 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/0401

Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

公开(公告)号：US20230307385A1

公开(公告)日：2023-09-28

申请号：US18325136

申请日：2023-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yang Yu ,  Jung-Wei Cheng ,  Yu-Min Liang ,  Jiun-Yi Wu ,  Yen-Fu Su ,  Chien-Chang Lin ,  Hsin-Yu Pan

IPC: H01L23/58 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/16 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/73204

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.