公开(公告)号：US20190385989A1

公开(公告)日：2019-12-19

申请号：US16009209

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.

公开(公告)号：US10510695B2

公开(公告)日：2019-12-17

申请号：US16219981

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

公开(公告)号：US10461034B2

公开(公告)日：2019-10-29

申请号：US15696192

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/36 ,  H01L21/48 ,  H01L21/56 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01Q1/22 ,  H01L21/683 ,  H01L23/498 ,  H01Q1/24

Abstract: A package structure and the method thereof are provided. At least one die is molded in a molding compound. A ground plate is located on a backside surface of the die, a first surface of the ground plate is exposed from the molding compound and a second surface of the ground plate is covered by the molding compound. The first surface of the ground plate is levelled and coplanar with a third surface of the molding compound. A connecting film is located between the backside surface of the die and the second surface of the ground plate. The die, the molding compound and the ground plate are in contact with the connecting film. Through interlayer vias (TIVs) are molded in the molding compound, and at least one of the TIVs is located on and physically contacts the second surface of the ground plate.

公开(公告)号：US20190035757A1

公开(公告)日：2019-01-31

申请号：US16022704

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

公开(公告)号：US20190035737A1

公开(公告)日：2019-01-31

申请号：US15696192

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/4889 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01Q1/2283 ,  H01Q1/243

Abstract: A package structure and the method thereof are provided. At least one die is molded in a molding compound. A ground plate is located on a backside surface of the die, a first surface of the ground plate is exposed from the molding compound and a second surface of the ground plate is covered by the molding compound. The first surface of the ground plate is levelled and coplanar with a third surface of the molding compound. A connecting film is located between the backside surface of the die and the second surface of the ground plate. The die, the molding compound and the ground plate are in contact with the connecting film. Through interlayer vias (TIVs) are molded in the molding compound, and at least one of the TIVs is located on and physically contacts the second surface of the ground plate.

公开(公告)号：US10177078B2

公开(公告)日：2019-01-08

申请号：US15372918

申请日：2016-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L21/56 ,  H01L23/485 ,  H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31

Abstract: Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed over the first protection layer. The chip package structure further includes a first photosensitive layer surrounding the first chip and covering the first chip and a redistribution layer formed over the first photosensitive layer.

公开(公告)号：US10157864B1

公开(公告)日：2018-12-18

申请号：US15662279

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is aside the die, and the RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer and a first RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a seed layer and a conductive layer. The seed layer surrounds sidewalls of the conductive layer, and is disposed between the conductive layer and the first dielectric layer.

公开(公告)号：US10074615B1

公开(公告)日：2018-09-11

申请号：US15794003

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Chih-Hua Chen ,  Hsiu-Jen Lin ,  Hao-Yi Tsai ,  Kuo-Chung Yee ,  Chia-Hung Liu

IPC: H01L23/552 ,  H01L23/34 ,  H01L23/538 ,  H01L21/02

Abstract: A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an insulating encapsulant is provided. The first semiconductor chip is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the first semiconductor chip is disposed on the at least one conductive plate and electrically connected to the redistribution layer. The conductive shielding structure is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the conductive shielding structure surrounds the first semiconductor chip and electrically connects the at least one conductive plate with the redistribution layer. The insulating encapsulant is disposed on the redistribution layer, encapsulating the first semiconductor chip, the conductive shielding structure, and surrounding the at least one conductive plate.

公开(公告)号：US20180012863A1

公开(公告)日：2018-01-11

申请号：US15202541

申请日：2016-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/683 ,  H01L21/768 ,  H01L27/146 ,  H01L25/00 ,  G06K9/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L25/0652 ,  G06K9/00006 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68331 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02333

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die.

公开(公告)号：US20170345761A1

公开(公告)日：2017-11-30

申请号：US15253897

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/66 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H01Q1/22 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01Q1/2283

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.