公开(公告)号：US5656842A

公开(公告)日：1997-08-12

申请号：US587788

申请日：1995-12-26

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue

IPC分类号： H01L21/336 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

CPC分类号： H01L29/78642 ,  H01L27/088 ,  H01L27/0928 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/4236

摘要： Semiconductor regions (2, 12) includes pillar-like projections (3, 13) extending vertically from major surfaces of the semiconductor regions and each having a vertical outer surface and an inner surface opposite to the outer surface. Vertical MOS transistors includes gate electrodes (4, 14) opposed to the outer surfaces of the pillar-like projections (3, 13) with gate insulating films (5, 15) interposed therebetween, with their bottom surfaces opposed to the major surfaces of the semiconductor regions (2, 12) with the gate insulating films (5, 15) interposed therebetween, source regions (6, 16) formed in upper end portions of the pillar-like projections (3, 13), drain regions (7, 17) formed in the major surfaces of the semiconductor regions (2, 12) so as to partly overlap bottom surfaces of the gate electrodes (4, 14), and back gate electrodes (8, 18) opposed to the inner surfaces of the pillar-like projections (3, 13) with back gate insulating films (9, 19) interposed therebetween. In the semiconductor device as above constructed, the MOS transistor can be supplied with a desired potential to avoid a punch through.

摘要翻译： 半导体区域（2,12）包括从半导体区域的主表面垂直延伸的每个具有垂直外表面和与外表面相对的内表面的柱状突起（3,13）。 垂直MOS晶体管包括与柱状突起（3,13）的外表面相对的栅电极（4,14），栅极绝缘膜（5,15）插入其间，其底表面与 具有介于其间的栅极绝缘膜（5,15）的半导体区域（2,12），形成在柱状突起（3,13）的上端部的源极区域（6,16），漏极区域（7,17） ）形成在所述半导体区域（2,12）的主表面上以部分地重叠所述栅电极（4,14）的底表面，以及与所述栅极电极（4）的内表面相对的背栅电极（8,18） 带有背栅绝缘膜（9,19）的凸起（3,13）。 在如上构造的半导体器件中，MOS晶体管可以被提供有期望的电位以避免穿通。

公开(公告)号：US5652453A

公开(公告)日：1997-07-29

申请号：US557247

申请日：1995-11-14

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.

摘要翻译： 可以获得能防止寄生晶体管形成的阈值电压降低的半导体装置。 在半导体器件中，在半导体层的侧壁上形成宽度向其下部增加的侧壁绝缘膜，并且形成栅极电极层，使得其在半导体层和侧壁绝缘膜上延伸 。

公开(公告)号：US5627390A

公开(公告)日：1997-05-06

申请号：US648828

申请日：1996-05-16

申请人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Inoue ,  Hirotada Kuriyama ,  Shigeto Maegawa ,  Kyozo Kanamoto ,  Toshiaki Iwamatsu

IPC分类号： H01L27/10 ,  H01L21/77 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/78642

摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

摘要翻译： 第一杂质扩散层形成源极/漏极区之一并且还形成位线。 形成源极/漏极区域中的另一个并且还形成存储节点的第一半导体层，沟道半导体层和第二半导体层设置在第一杂质扩散层上。 电容绝缘膜设置在第二导电层上。 电池板设置在存储节点上，其间具有电容器绝缘膜。 位线的电容减小，并且由此构成的动态随机存取存储器执行高速操作。

公开(公告)号：US07692243B2

公开(公告)日：2010-04-06

申请号：US11870610

申请日：2007-10-11

申请人： Toshiaki Iwamatsu

发明人： Toshiaki Iwamatsu

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78615

摘要： The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.

摘要翻译： 本发明的目的在于提供具有高速度，低功率的结构的半导体器件，并且可以高度集成。 本发明是形成在SOI衬底中的半导体器件，其中BOX层和SOI层被层压在硅衬底上。 并且本发明设置有FIN型晶体管，栅极电极围绕形成在SOI层中的体区域卷绕，并且使用部分隔离和完全隔离与元件隔离分离的平面型晶体管，并形成在 SOI层。

公开(公告)号：US20080261387A1

公开(公告)日：2008-10-23

申请号：US12143868

申请日：2008-06-23

申请人： Takashi IPPOSHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Takashi IPPOSHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L21/265

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。

公开(公告)号：US07402865B2

公开(公告)日：2008-07-22

申请号：US11210666

申请日：2005-08-25

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。

公开(公告)号：US20080128814A1

公开(公告)日：2008-06-05

申请号：US12003273

申请日：2007-12-21

申请人： Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Yuuichi Hirano ,  Takashi Ipposhi

IPC分类号： H01L27/088

CPC分类号： H01L29/78615 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78609

摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

摘要翻译： 在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即， （隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。

公开(公告)号：US07358555B2

公开(公告)日：2008-04-15

申请号：US11409040

申请日：2006-04-24

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Tatsuhiko Ikeda ,  Shigeto Maegawa

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Tatsuhiko Ikeda ,  Shigeto Maegawa

IPC分类号： H01L27/108

CPC分类号： H01L27/0811 ,  H01L27/1203

摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered.Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.

摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。

公开(公告)号：US07352049B2

公开(公告)日：2008-04-01

申请号：US11500340

申请日：2006-08-08

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/00

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层3上，以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

公开(公告)号：US20080032486A1

公开(公告)日：2008-02-07

申请号：US11868143

申请日：2007-10-05

申请人： Toshiaki Iwamatsu ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Shigenobu Maeda

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer manufacturing method comprising the steps of preparing a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions, preparing a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction of one of said plurality of cuts of said first semiconductor wafer, bonding said first and second semiconductor wafers to each other while using said one of said plurality of cuts of said first semiconductor wafer and said cut of said second semiconductor wafer in order to position said first and second semiconductor wafers, with another one of said plurality of cuts of said first semiconductor wafer being engaged with a guide portion of a semiconductor wafer manufacturing apparatus, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other, and forming the portion implanted with the oxygen ions into an oxide film layer by a thermal treatment.

摘要翻译： 一种半导体晶片制造方法，包括以下步骤：制备在晶体方向上形成有多个切口的第一半导体晶片，所述第一半导体晶片具有在晶体方向上不同晶体的边缘部分处形成的切口的第二半导体晶片 所述第一半导体晶片的所述多个切口中的一个切口的方向，将所述第一和第二半导体晶片彼此接合，同时使用所述第一半导体晶片的所述多个切口和所述第二半导体晶片的所述切口中的所述一个切口以便定位 所述第一和第二半导体晶片，所述第一半导体晶片的所述多个切口中的另一个与半导体晶片制造设备的引导部分接合，使所述第一半导体晶片变薄，将氧离子从所述第一半导体晶片侧注入到 所述第一和第二半导体晶片的部分附近 e彼此键合，并且通过热处理将注入氧离子的部分形成氧化物膜层。