公开(公告)号：US09748349B2

公开(公告)日：2017-08-29

申请号：US14723467

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Wei-Hao Huang

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/518 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

公开(公告)号：US20170125291A1

公开(公告)日：2017-05-04

申请号：US15404163

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

公开(公告)号：US09385000B2

公开(公告)日：2016-07-05

申请号：US14162755

申请日：2014-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/76816

Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.

Abstract translation: 提供了一种执行蚀刻工艺的方法。 提供了一种衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 在基板上形成包括有机层，底部防反射涂层（BARC）和光致抗蚀剂层的三层结构。 去除第二区域中的光致抗蚀剂层和BARC。 通过使用BARC和/或光致抗蚀剂层作为掩模，进行蚀刻工艺以去除第二区域中的有机层，其中蚀刻工艺使用蚀刻剂包括CO 2。

公开(公告)号：US20160172300A1

公开(公告)日：2016-06-16

申请号：US14591936

申请日：2015-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构上形成牺牲层; 在牺牲层和ILD层中形成第一接触塞; 去除牺牲层; 以及在所述栅极结构和所述第一接触插塞上形成第一电介质层。

公开(公告)号：US09337084B1

公开(公告)日：2016-05-10

申请号：US14846822

申请日：2015-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Kun-Yuan Liao ,  Chun-Lung Chen ,  Ching-Pin Hsu ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/76801 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract translation: 本发明提供了一种用于制造半导体器件的接触孔的方法，包括第一介电层，第一介电层和第二区分别形成在第一介电层上，形成至少两个切割硬掩模， 第一区域和第二区域分别设置在切割硬掩模正下方的至少两个台阶部分。 之后，形成在第一区域内的至少一个第一狭槽开口，其中第一狭槽开口部分地与切割硬掩模重叠并且直接接触切割硬掩模，并且在第二区域内形成至少一个第二接触开口， 第二接触开口不直接接触切割硬掩模，并且形成至少两个接触孔，其中每个接触孔穿过每个台阶高度部分。

公开(公告)号：US09312258B2

公开(公告)日：2016-04-12

申请号：US13936214

申请日：2013-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Ling-Chun Chou ,  I-Chang Wang ,  Shin-Chuan Huang ,  Jiunn-Hsiung Liao ,  Shin-Chi Chen ,  Pau-Chung Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chieh-Te Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

公开(公告)号：US20160020144A1

公开(公告)日：2016-01-21

申请号：US14332375

申请日：2014-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/532 ,  H01L21/311 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a device thereon; forming a dielectric layer on the device and the substrate; forming a first mask layer on the dielectric layer; removing part of the first mask layer and part of the dielectric layer for forming a patterned first mask layer on the dielectric layer; covering a hard mask on the patterned first mask layer and the dielectric layer; partially removing the hard mask for forming a spacer adjacent to the patterned first mask layer and the dielectric layer; forming a contact hole adjacent to the spacer; filling the contact hole with a metal layer; and planarizing the metal layer for forming a contact plug, wherein the contact plug contacts the dielectric layer and the spacer simultaneously.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个装置的基板; 在所述器件和所述衬底上形成介电层; 在所述电介质层上形成第一掩模层; 去除所述第一掩模层的一部分和所述电介质层的一部分，以在所述电介质层上形成图案化的第一掩模层; 覆盖图案化的第一掩模层和电介质层上的硬掩模; 部分去除用于形成邻近图案化的第一掩模层和电介质层的隔离物的硬掩模; 形成与间隔件相邻的接触孔; 用金属层填充接触孔; 以及平坦化用于形成接触插塞的金属层，其中所述接触插塞同时接触所述电介质层和所述间隔物。

公开(公告)号：US09165997B2

公开(公告)日：2015-10-20

申请号：US14583122

申请日：2014-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

IPC: H01L21/20 ,  H01L21/332 ,  H01L49/02 ,  H01L27/06 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

Abstract translation: 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US08962490B1

公开(公告)日：2015-02-24

申请号：US14048043

申请日：2013-10-08

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Chieh-Te Chen

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L29/66477

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底，其中至少一个金属栅极形成在ILD层中，并且至少一个源极/漏极区域邻近金属栅极的两侧; 在ILD层上形成第一介电层; 在所述第一电介质层上形成第二电介质层; 执行第一蚀刻工艺以部分地去除所述第二介电层; 利用第一清洁剂进行第一次湿清洁处理; 执行第二蚀刻工艺以部分地去除所述第一介电层; 并且利用第二清洁剂进行第二湿式清洁处理，其中所述第一清洁剂与所述第二清洁剂不同。

公开(公告)号：US08916475B1

公开(公告)日：2014-12-23

申请号：US14070262

申请日：2013-11-01

Applicant: United Microelectronics Corp.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Cheng-Hsing Chuang

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823431

Abstract: A patterning method is provided. A mask composite layer and a first tri-layer photoresist are sequentially formed on a target layer. A first etching is performed to the mask composite layer, using the first tri-layer photoresist as a mask, to form at least one first opening in an upper portion of the mask composite layer. The first tri-layer photoresist is removed. A second tri-layer photoresist is formed on the mask composite layer. A second etching is performed to the mask composite layer, using the second tri-layer photoresist as a mask, to form at least one second opening in the upper portion of the mask composite layer. The second tri-layer photoresist is removed. A lower portion of the mask composite layer is patterned by using the upper portion of the mask composite layer as a mask. The target layer is patterned by using the patterned mask composite layer as a mask.

Abstract translation: 提供了图案化方法。 在目标层上依次形成掩模复合层和第一三层光致抗蚀剂。 使用第一三层光致抗蚀剂作为掩模对掩模复合层进行第一蚀刻，以在掩模复合层的上部中形成至少一个第一开口。 去除第一三层光致抗蚀剂。 在掩模复合层上形成第二三层光致抗蚀剂。 使用第二三层光致抗蚀剂作为掩模对掩模复合层进行第二蚀刻，以在掩模复合层的上部形成至少一个第二开口。 去除第二三层光致抗蚀剂。 通过使用掩模复合层的上部作为掩模来对掩模复合层的下部进行图案化。 通过使用图案化掩模复合层作为掩模来对目标层进行图案化。