公开(公告)号：US20210210555A1

公开(公告)日：2021-07-08

申请号：US17124457

申请日：2020-12-16

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: Provided is a resistive random-access memory device, including: multiple pillars, extending in a vertical direction with respect to a main surface of a substrate; multiple bit lines, extending in a horizontal direction with respect to the main surface of the substrate; and a memory cell, formed at an intersection of the pillars and the bit lines. The memory cell includes a gate insulating film formed on an outer periphery of the pillars, a semiconductor film formed on an outer periphery of the gate insulating film and providing a channel region, and a variable resistance element formed on a part of an outer periphery of the semiconductor film. An electrode region of an outer periphery of the variable resistance element is connected to one of a pair of adjacent bit lines, and the semiconductor film is connected to the other of the pair of adjacent bit lines.

公开(公告)号：US20210158869A1

公开(公告)日：2021-05-27

申请号：US16860022

申请日：2020-04-27

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: G11C13/00

Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).

公开(公告)号：US10811425B2

公开(公告)日：2020-10-20

申请号：US15892350

申请日：2018-02-08

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Riichiro Shirota

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

公开(公告)号：US20200303384A1

公开(公告)日：2020-09-24

申请号：US16893411

申请日：2020-06-04

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Riichiro Shirota

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L29/792

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

公开(公告)号：US20180166147A1

公开(公告)日：2018-06-14

申请号：US15826698

申请日：2017-11-30

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: G11C29/38 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C29/38 ,  G11C7/04 ,  G11C7/20 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C2013/0083 ,  G11C2029/0407

Abstract: A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure includes a built-in self-test circuit 110 and a resistive random-access memory. The built-in self-test circuit 110 includes a reforming information setting part 230 for performing reforming of the resistive random-access memory. When the operation of a forming execution part 220 or a test execution part 210 is performed, a flag is set to “1” for the reforming information setting part 230. Moreover, when a power supply mounted on a circuit board by IR reflow is turned on, the built-in self-test control part 200 references the flag of the reforming information setting part 230, and if the flag is “1”, then the forming execution part 220 executes the reforming of the resistive random-access memory.

公开(公告)号：US09935116B2

公开(公告)日：2018-04-03

申请号：US15672298

申请日：2017-08-09

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Pin-Yao Wang

IPC: H01L21/311 ,  H01L27/11524 ,  H01L29/66 ,  H01L21/308 ,  G11C16/12 ,  H01L21/28 ,  G11C8/14 ,  H01L21/306

CPC classification number: H01L27/11524 ,  G11C8/14 ,  G11C16/12 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/66553 ,  H01L29/66825

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

公开(公告)号：US09627094B2

公开(公告)日：2017-04-18

申请号：US15202578

申请日：2016-07-06

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: G11C11/34 ,  G11C29/00 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C29/76 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3404 ,  G11C16/3459 ,  G11C29/82

Abstract: A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.

公开(公告)号：US20170011809A1

公开(公告)日：2017-01-12

申请号：US15202578

申请日：2016-07-06

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: G11C29/00 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C29/76 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3404 ,  G11C16/3459 ,  G11C29/82

Abstract: A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.

Abstract translation: 本发明的修复方法包括以下步骤：存储包括坏列的地址的冗余信息，用于识别错误列的偶数列或奇数列中的哪一个和冗余地址的故障的识别信息 用于修复不良列的冗余内存区列; 基于冗余信息确定所选列的列地址是否与坏列的地址一致; 当一致时，基于识别信息将具有故障的坏列的列转换成冗余列的列; 并且不将不良列的另一列转换为冗余列的另一列。

公开(公告)号：US20150155043A1

公开(公告)日：2015-06-04

申请号：US14332405

申请日：2014-07-16

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0441 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

Abstract: The invention provides a NAND-type semiconductor memory device capable of high speed operation. A semiconductor memory device of the invention includes: a memory array, which forms a plurality of memory cells arranged in a matrix direction; a vertical selecting mechanism, which couples to the memory array, and selects the memory cells in a vertical direction of the memory array according to a vertical address signal; a horizontal selecting mechanism, which couples to the memory array, and selects the memory cells in a horizontal direction of the memory array according to a horizontal address signal; and a controlling mechanism, which reads data from the memory cells or writes data into the memory cells. A plurality of cell units is disposed in the memory array. Each cell unit is consisted of a data memory cell which storages data and a reference memory cell which storages reference data.

Abstract translation: 本发明提供能够进行高速操作的NAND型半导体存储器件。 本发明的半导体存储器件包括：形成沿矩阵方向布置的多个存储单元的存储器阵列; 垂直选择机构，其耦合到存储器阵列，并根据垂直地址信号选择存储器阵列的垂直方向上的存储单元; 水平选择机构，其耦合到存储器阵列，并根据水平地址信号在存储器阵列的水平方向上选择存储单元; 以及从存储单元读取数据或将数据写入存储单元的控制机构。 多个单元单元设置在存储器阵列中。 每个单元单元由存储数据的数据存储单元和存储参考数据的参考存储单元组成。