公开(公告)号：US06404274B1

公开(公告)日：2002-06-11

申请号：US09289413

申请日：1999-04-09

申请人： Koji Hosono ,  Yasuo Itoh ,  Ken Takeuchi

发明人： Koji Hosono ,  Yasuo Itoh ,  Ken Takeuchi

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  G11C16/30 ,  H02M2001/0025

摘要： There is provided an internal voltage generating circuit for outputting positive multi-level voltages by using a current addition type D/A conversion circuit, and suppressing increase of the pattern area of a resistor network even if the number of bits of a digital input increases. This circuit includes a load resistor element having one terminal connected to the output node of a voltage generating circuit, a first voltage setting circuit which is connected to a first node to which the other terminal of the load resistor element is connected and controls the magnitude of an input current from the load resistor element by controlling an equivalent resistor in accordance with digital data, a second voltage setting circuit which is connected to the first node and into which a predetermined current flows from the load resistor element, a potential comparison circuit for detecting a potential at the first node by comparing the potential at the first node with a reference potential, and a voltage control circuit for setting the potential at the first node to become equal to the reference potential by substantially controlling the voltage generating circuit in accordance with an output from the circuit.

摘要翻译： 提供了一种内部电压产生电路，用于通过使用电流相加型D / A转换电路输出正的多电平电压，并且即使数字输入的位数增加，也抑制了电阻网络的图形区域的增加。 该电路包括负载电阻元件，其一端连接到电压产生电路的输出节点，第一电压设置电路连接到负载电阻元件的另一端连接到的第一节点， 通过根据数字数据控制等效电阻器，来自负载电阻元件的输入电流;连接到第一节点的第二电压设置电路，预定电流从负载电阻器元件流过的电压设定电路;用于检测的电位比较电路 通过将第一节点处的电位与参考电位进行比较来确定第一节点处的电位;以及电压控制电路，用于通过基本上控制电压产生电路来将第一节点处的电位设置为等于参考电位 从电路输出。

公开(公告)号：US6107658A

公开(公告)日：2000-08-22

申请号：US468928

申请日：1999-12-22

申请人： Yasuo Itoh ,  Koji Sakui

发明人： Yasuo Itoh ,  Koji Sakui

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/72

CPC分类号： H01L27/115 ,  G11C16/0483

摘要： In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

摘要翻译： 在使用本地自增强系统的NAND EEPROM中，将允许与所选存储单元相邻的存储单元导通的中间电压被施加到相邻存储单元的控制栅极。 因此，即使相邻的存储单元处于常关状态，也可以将位线的电位发送到相邻的存储单元。 因此，提高了在非选择的NAND存储单元列中写入禁止的可靠性，同时可以将数据随机写入到所选NAND存储单元列中的多个存储单元中。 当要擦除数据时，施加到控制栅极的擦除电压的绝对值可以较小。 结果，可以通过比传统技术中所需的更低的擦除电压来擦除数据。 因此，可以进一步提高元素精化，可靠性和产率。

公开(公告)号：US6081454A

公开(公告)日：2000-06-27

申请号：US145466

申请日：1998-09-02

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。 每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。 存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。 当在数据编程模式下将数据一次写入所选择的存储单元中时，将特定的偏置电压施加到所选择的单元，从而验证所选存储单元的实际电数据写入状态。 如果比较器检测到验证的写入条件不满意，则通过向所选择的单元格额外提供补偿所选择的存储单元晶体管中的验证的写入条件的不满足的适当电压来重复执行数据重写操作。

公开(公告)号：US6061289A

公开(公告)日：2000-05-09

申请号：US406731

申请日：1999-09-28

申请人： Yasuo Itoh ,  Sumio Tanaka

发明人： Yasuo Itoh ,  Sumio Tanaka

IPC分类号： G11C16/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/76 ,  H03M1/78 ,  G11C7/00 ,  G11C16/04

CPC分类号： H03M1/68 ,  H03M1/785 ,  H03M1/76

摘要： A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

摘要翻译： 可变电位发生电路包括电阻分压器电路和第一和第二运算放大器。 电阻分压器电路包括在电源节点和接地节点之间串联连接的开关元件和电流调节型数字/模拟转换器电路。 电阻分压器电路具有第一节点，在该第一节点处出现通过对从可变电位输出节点输出的可变电位的电阻划分获得的分压电位和施加虚拟电位的第二节点。 第一运算放大器将第一节点的分压电位与参考电位进行比较，以实现用于设置等于参考电位的可变输出电位的反馈控制。 第二运算放大器将第二节点的虚拟电位与参考电位进行比较，以实现用于设置虚拟电位等于参考电位的反馈控制。

公开(公告)号：US6023424A

公开(公告)日：2000-02-08

申请号：US213411

申请日：1998-12-17

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

公开(公告)号：US6016274A

公开(公告)日：2000-01-18

申请号：US044989

申请日：1998-03-20

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454 ,  G11C5/147

摘要： The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied. The control circuit controls the dividing circuit such as to set the write voltage indicated by the write voltage data in the memory element in the write mode. Thus, the write voltage is optimized, and the appropriate number of times of write can be performed.

摘要翻译： 本发明的半导体存储器件包括具有浮置栅极和控制栅极的存储单元，用于通过偏移阈值来保持数据。 在测试模式下，通过验证电路验证从存储单元读取的数据。 如果验证结果未被批准，则再次执行数据写入。 这种写入的次数由计数电路计数。 在数据表中，存储写入和写入电压次数之间的各种相关性。 从数据表中选择性地输出与计数电路的写入次数对应的写入电压数据。 写入电压将写入电压数据写入存储元件。 用于改变写入电压的电压限制电路另一端的电压被分成几个电压，因此可以改变写入电压。 控制电路控制分频电路，以将写入电压数据所指示的写入电压设置在写入模式中的存储元件中。 因此，写入电压被优化，并且可以执行适当的写入次数。

公开(公告)号：US5990977A

公开(公告)日：1999-11-23

申请号：US845705

申请日：1997-04-25

申请人： Isami Kaneda ,  Yasuo Itoh

发明人： Isami Kaneda ,  Yasuo Itoh

IPC分类号： H04N5/78 ,  H04N5/262 ,  H04N5/775 ,  H04N5/85 ,  H04N5/91 ,  H04N9/74 ,  H04N9/804

CPC分类号： H04N9/74 ,  H04N9/8042 ,  H04N5/445 ,  H04N5/775 ,  H04N5/85

摘要： A picture switching apparatus for executing a fade-out/fade-in processing between adjacent video recording files includes a multiplier for multiplying a decoded video data with a multiplication coefficient (1-km), a multiplier for multiplying an output data of a data output circuit with a multiplication coefficient km and a data synthesizer for summing results of multiplication from the respective multipliers. The picture switching apparatus thus constructed performs the fade-out/fade-in processing without modification of the original video data for fading processing, by controlling km at the junction between the files such that the mining ratio of the color data for fading to a decoded color data is gradually increased/decreased.

摘要翻译： 一种用于在相邻视频记录文件之间执行淡出/淡入淡出处理的画面切换装置，包括用于将解码视频数据与乘法系数（1-km）相乘的乘法器，用于将数据输出的输出数据相乘的乘法器 具有乘法系数km的电路和用于对来自相应乘法器的乘法结果求和的数据合成器。 这样构成的图像切换装置通过控制文件之间的连接处的km，使得淡入淡出的彩色数据的采样率与经解码的图像切换装置进行淡入/淡出处理，而不改变用于衰落处理的原始视频数据 颜色数据逐渐增加/减少。

公开(公告)号：US5880994A

公开(公告)日：1999-03-09

申请号：US909727

申请日：1997-08-12

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线和线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。

公开(公告)号：US5818791A

公开(公告)日：1998-10-06

申请号：US826152

申请日：1997-03-27

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

公开(公告)号：US5784315A

公开(公告)日：1998-07-21

申请号：US402055

申请日：1995-03-10

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454 ,  G11C5/147

摘要： The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied. The control circuit controls the dividing circuit such as to set the write voltage indicated by the write voltage data in the memory element in the write mode. Thus, the write voltage is optimized, and the appropriate number of times of write can be performed.