公开(公告)号：USD696100S1

公开(公告)日：2013-12-24

申请号：US29396128

申请日：2011-06-27

申请人： Makoto Wada ,  Koji Katsuta

设计人： Makoto Wada ,  Koji Katsuta

公开(公告)号：US08507138B2

公开(公告)日：2013-08-13

申请号：US12456243

申请日：2009-06-12

申请人： Kouichi Yamada ,  Kazunori Fukuma ,  Makoto Wada

发明人： Kouichi Yamada ,  Kazunori Fukuma ,  Makoto Wada

IPC分类号： H01M8/04 ,  F04F5/48

CPC分类号： H01M8/04089 ,  F04F5/18 ,  F04F5/36 ,  F04F5/463 ,  Y10T137/2572

摘要： An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.

公开(公告)号：US08410608B2

公开(公告)日：2013-04-02

申请号：US13233312

申请日：2011-09-15

申请人： Makoto Wada ,  Yuichi Yamazaki

发明人： Makoto Wada ,  Yuichi Yamazaki

IPC分类号： H01L23/48

CPC分类号： H01L23/53276 ,  B82Y10/00 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion.

摘要翻译： 根据一个实施例，一种器件包括具有第一沟槽的绝缘层，第一沟槽中的第一互连层，包括铜的第一互连层，并包括凹部，以及在凹部的内表面上的第一石墨烯片 。

公开(公告)号：US08378335B2

公开(公告)日：2013-02-19

申请号：US13075591

申请日：2011-03-30

申请人： Yuichi Yamazaki ,  Makoto Wada ,  Tadashi Sakai

发明人： Yuichi Yamazaki ,  Makoto Wada ,  Tadashi Sakai

IPC分类号： H01L29/06

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  H01L21/02491 ,  H01L21/02527 ,  H01L29/45 ,  H01L29/66015 ,  H01L29/76

摘要： A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug is connected to the graphene film. The adjustment film is formed in a region other than a region connected to the contact plug of a surface of the graphene film to adjust a Dirac point position in a same direction as the region connected to the contact plug with respect to a Fermi level.

摘要翻译： 根据实施例的半导体器件包括催化金属膜，石墨烯膜，接触插塞和调整膜。 催化金属膜形成在基板的上方。 在催化金属膜上形成石墨烯膜。 接触塞连接到石墨烯膜。 调整膜形成在与石墨烯膜的表面的接触插塞连接的区域以外的区域中，以相对于费米能级与连接到接触插塞的区域相同的方向调节狄拉克点位置。

公开(公告)号：US08198193B2

公开(公告)日：2012-06-12

申请号：US13041543

申请日：2011-03-07

申请人： Naoshi Sakuma ,  Tadashi Sakai ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Mariko Suzuki ,  Makoto Wada

发明人： Naoshi Sakuma ,  Tadashi Sakai ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Mariko Suzuki ,  Makoto Wada

IPC分类号： H01L21/4763

CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor substrate includes the following steps: forming a first wiring layer on a substrate; forming an interlayer insulating film having a via hole on the wiring layer; forming carbon nanotubes in the via hole; performing a fluorination treatment entirely to the substrate; forming an embedded film in the via hole having the carbon nanotubes therein; and polishing the substrate to entirely flatten the substrate.

摘要翻译： 半导体衬底的制造方法包括以下步骤：在衬底上形成第一布线层; 在所述布线层上形成具有通孔的层间绝缘膜; 在通孔中形成碳纳米管; 完全对基材进行氟化处理; 在其中具有碳纳米管的通孔中形成嵌入膜; 并抛光衬底以使衬底完全平坦化。

公开(公告)号：US08169085B2

公开(公告)日：2012-05-01

申请号：US12696276

申请日：2010-01-29

申请人： Yousuke Akimoto ,  Makoto Wada

发明人： Yousuke Akimoto ,  Makoto Wada

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/76876 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S977/72 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring.

摘要翻译： 根据一个实施例的半导体器件包括：衬底; 设置在所述基板上方并且包括石墨烯纳米纤维层的布线，所述石墨烯纳米纤维层包括多个层叠的石墨烯纳米薄片; 以及布线连接构件，其穿透所述多个石墨烯纳米纤维板中的至少一个，用于将所述布线连接到所述布线上方或下方的导电构件。

公开(公告)号：US20120080662A1

公开(公告)日：2012-04-05

申请号：US13216445

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L29/15 ,  H01L21/283

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

摘要翻译： 根据一个实施例，石墨烯互连包括第一绝缘膜，第一催化剂膜和第一石墨烯层。 第一绝缘膜包括互连沟槽。 在互连沟槽的两个侧表面上的第一绝缘膜上形成第一催化剂膜。 第一石墨烯层形成在互连沟槽的两个侧表面上的第一催化剂膜上，并且包括沿垂直于两个侧表面的方向堆叠的石墨烯片。

公开(公告)号：US07943517B2

公开(公告)日：2011-05-17

申请号：US11877243

申请日：2007-10-23

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 一种制造半导体器件的方法，包括在设置在半导体衬底上的层间绝缘膜中形成开口，形成含有预定金属元素的辅助膜以覆盖开口的内表面，形成主膜以填充开口 在形成辅助膜之后，主膜含有用作互连主层的材料的Cu，并且在形成主膜之前或之后进行热处理，从而扩散辅助膜的预定金属元素 在面向辅助膜的层间绝缘膜的表面上，以在开口内的层间绝缘膜上形成阻挡膜，所述阻挡膜以预定的金属元素与成分元素为主要成分， 的层间绝缘膜。

公开(公告)号：US20090191712A1

公开(公告)日：2009-07-30

申请号：US12208010

申请日：2008-09-10

申请人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

发明人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/308

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.

摘要翻译： 在本发明的一个方面中，制造半导体器件的方法可以包括在待图案化的非晶硅层上形成第一膜，第一膜和非线性膜的线间距比约为3:1 ，在对第一膜进行处理之后，将该图案的线部分从线部分的两个纵向侧线直到线部分的宽度减小到大约三分之一，在下一步处理之后，将非晶硅层的一部分重新形成第一膜 不能使重整部分具有不同的蚀刻比，并除去除了重整部分以外的第一膜和非晶硅层。

公开(公告)号：US20050218519A1

公开(公告)日：2005-10-06

申请号：US11063876

申请日：2005-02-24

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 半导体器件包括设置在半导体衬底上并具有形成在其中的开口的层间绝缘膜。 将包含Cu作为主要成分的互连主层嵌入开口部。 隔离膜介于开口内的层间绝缘膜和互连主层之间。 作为主要成分，阻挡膜含有具有层间绝缘膜的成分元素的预定金属元素的化合物。