公开(公告)号：US20110014574A1

公开(公告)日：2011-01-20

申请号：US12894633

申请日：2010-09-30

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： G03F7/20

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/11521

摘要： Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.

摘要翻译： 公开了形成用于集成电路的导电和/或半导体特征的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。 常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线接触。

公开(公告)号：US20110008970A1

公开(公告)日：2011-01-13

申请号：US12886459

申请日：2010-09-20

申请人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej S. Sandhu ,  Luan C. Tran

发明人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej S. Sandhu ,  Luan C. Tran

IPC分类号： H01L21/31

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/76232 ,  H01L27/105 ,  H01L27/1052

摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.

摘要翻译： 本发明包括形成用于半导体结构的隔离区域的方法。 可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。 可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。 第一个开口用含碳材料的共形层变窄。 穿过保形层以沿着狭窄的开口的底部露出衬底。 去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。 然后从第一开口内去除含碳材料，并且电绝缘材料形成在第一和第二开口内。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

公开(公告)号：US07659161B2

公开(公告)日：2010-02-09

申请号：US11111360

申请日：2005-04-21

申请人： Luan C. Tran ,  Fred D. Fishburn

发明人： Luan C. Tran ,  Fred D. Fishburn

IPC分类号： H01L21/00

CPC分类号： H01L27/10888 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/24 ,  Y10S257/906 ,  Y10S257/908

摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.

摘要翻译： 本发明包括可用于形成存储器阵列的存储器阵列和方法。 在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。 可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。 可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。 在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。 然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

公开(公告)号：US07288806B2

公开(公告)日：2007-10-30

申请号：US11111605

申请日：2005-04-21

申请人： Luan C. Tran ,  Fred D. Fishburn

发明人： Luan C. Tran ,  Fred D. Fishburn

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/24 ,  Y10S257/906 ,  Y10S257/908

摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.

摘要翻译： 本发明包括可用于形成存储器阵列的存储器阵列和方法。 在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。 可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。 可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。 在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。 然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

公开(公告)号：US07279740B2

公开(公告)日：2007-10-09

申请号：US11127618

申请日：2005-05-12

申请人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

发明人： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

摘要： Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

摘要翻译： 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US07221020B2

公开(公告)日：2007-05-22

申请号：US11000003

申请日：2004-12-01

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide area for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

摘要翻译： 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：US06977421B2

公开(公告)日：2005-12-20

申请号：US10371689

申请日：2003-02-20

申请人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

发明人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

IPC分类号： H01L21/28 ,  H01L21/8242 ,  H01L27/105 ,  H01L29/80

CPC分类号： H01L27/10873 ,  H01L21/28123 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10894

摘要： The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

摘要翻译： 本发明包括其中具有结构的DRAM阵列，其包括通过中间绝缘材料与第二材料分离的第一材料。 第一种材料被掺杂至至少1×10 17个原子/ cm 3与n型和p型掺杂剂。 本发明还包括半导体结构，其中掺杂材料在衬底的一段上方。 掺杂材料在其中具有第一类型多数掺杂剂，并且与电接地电连接。 一对导电掺杂的扩散区域与该段相邻，并且通过该段的至少一部分彼此间隔开。 导电掺杂扩散区域中具有第二类型多数掺杂剂。 本发明还包括形成半导体结构的方法。

公开(公告)号：US06946353B2

公开(公告)日：2005-09-20

申请号：US10831192

申请日：2004-04-26

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

摘要翻译： 一种用于调节低电压高速半导体器件的寄生电容最小化的方法。 该方法使用阴影效应和倾斜冲击穿过垂直结构之间的预防植入物来提供分级植入物。 植入角度大于或等于S / H的反正切，其中S是水平距离，H是这种垂直结构的高度。

公开(公告)号：US06825077B2

公开(公告)日：2004-11-30

申请号：US10713647

申请日：2003-11-13

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

摘要： The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

摘要翻译： 本发明包括形成在半导体衬底上的6F 2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06806137B2

公开(公告)日：2004-10-19

申请号：US10705707

申请日：2003-11-11

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

摘要翻译： 诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。 导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。 位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。