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公开(公告)号：US11366633B2
公开(公告)日：2022-06-21
申请号：US16017800
申请日：2018-06-25
Applicant: AVNERA CORPORATION
Inventor： Shawn O'Connor , Eric Sorensen , Manpreet S. Khaira , Sydney Newton
Abstract: An apparatus can include an audio playback device configured to provide an audio output to a user, and a controller configured to: receive an initial playback position within the audio output; determine that an off-ear event has occurred; identify a time corresponding to the off-ear event; instruct the audio playback device to pause the audio output at the identified time; and calculate a new playback position within the audio output based at least in part on the identified time.
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公开(公告)号：US10650797B2
公开(公告)日：2020-05-12
申请号：US16404514
申请日：2019-05-06
Applicant: Avnera Corporation
Inventor： Amit Kumar
IPC: G10K11/175 , G10K11/178
Abstract: The disclosure includes an acoustic processing network comprising a Digital Signal Processor (DSP) operating at a first frequency and a Real-Time Acoustic Processor (RAP) operating at a second frequency higher than the first frequency. The DSP receives a noise signal from at least one microphone. The DSP then generates a noise filter based on the noise signal. The RAP receives the noise signal from the microphone and the noise filter from the DSP. The RAP then generates an anti-noise signal based on the noise signal and the noise filter for use in Active Noise Cancellation (ANC).
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63.发明授权公开(公告)号：US10574254B2
公开(公告)日：2020-02-25
申请号：US16173398
申请日：2018-10-29
Applicant: Avnera Corporation
Inventor： Wai Lee , Jianping Wen , Garry N. Link
Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
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公开(公告)号：US10403279B2
公开(公告)日：2019-09-03
申请号：US15706178
申请日：2017-09-15
Applicant: Avnera Corporation
Inventor： Xudong Zhao , Alexander C. Stange , Shawn O'Connor , Ali Hadiashar
Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.
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65.发明授权公开(公告)号：US10263629B2
公开(公告)日：2019-04-16
申请号：US15991871
申请日：2018-05-29
Applicant: Avnera Corporation
Inventor： Jianping Wen , Gordon Ueki
Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.
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Patent Agency Ranking
公开(公告)号：US10038548B2
公开(公告)日：2018-07-31
申请号：US15799473
申请日：2017-10-31
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US09894438B2
公开(公告)日：2018-02-13
申请号：US15294556
申请日：2016-10-14
Applicant: Avnera Corporation
Inventor： Amit Kumar , Thomas Irrgang , Xudong Zhao
IPC: A61F11/06 , H04R3/00 , G10K11/178
CPC classification number: H04R3/005 , G10K11/178 , G10K2210/3028 , G10K2210/3051 , G10K2210/3056 , H04R1/1083 , H04R2410/05
Abstract: An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.
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公开(公告)号：US09831887B2
公开(公告)日：2017-11-28
申请号：US15391573
申请日：2016-12-27
Applicant: Avnera Corporation
Inventor： Jianping Wen , Garry Link , Wai Lee
CPC classification number: H03M1/1009 , H03M1/0682 , H03M1/0692 , H03M1/38 , H03M1/403 , H03M1/462 , H03M1/468 , H03M1/804
Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.
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公开(公告)号：US09741333B2
公开(公告)日：2017-08-22
申请号：US14148533
申请日：2014-01-06
Applicant: Avnera Corporation
Inventor： Amit Kumar , Wai Lang Lee , Jianping Wen
IPC: G10K11/16 , G10K11/178
CPC classification number: G10K11/178 , G10K11/17853 , G10K11/17873 , G10K11/17875 , G10K11/17879 , G10K2210/3016 , G10K2210/3026 , G10K2210/3027 , G10K2210/3028 , H04R2460/01
Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.
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公开(公告)号：US09699560B2
公开(公告)日：2017-07-04
申请号：US15365795
申请日：2016-11-30
Applicant: Avnera Corporation
Inventor： Theodore Hetke , John Speth
CPC classification number: H04R3/12 , H04R2420/07 , H04R2420/09 , H04R2430/01 , H04W4/80
Abstract: A method for forming a complete ring network of a plurality of Bluetooth® speakers, the method including populating a configurable speaker register of each of the plurality of Bluetooth® speakers with an address of an upstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, populating the configurable speaker register of each of the plurality of Bluetooth® speakers with an address of a downstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, and coupling an audio source to one Bluetooth® speaker of the plurality of Bluetooth® speakers.
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