公开(公告)号：US09438031B2

公开(公告)日：2016-09-06

申请号：US14379908

申请日：2012-02-29

Applicant: Patrice Besse ,  Jerome Casters ,  Jean-Philippe Laine ,  Alain Salles

Inventor： Patrice Besse ,  Jerome Casters ,  Jean-Philippe Laine ,  Alain Salles

IPC: H02H3/22 ,  H02H9/02 ,  H02M7/5387 ,  H05K1/02 ,  H01L27/02 ,  H02H9/04

CPC classification number: H02H9/02 ,  H01L27/0266 ,  H02H9/042 ,  H02H9/046 ,  H02M7/5387 ,  H05K1/0259

Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.

Abstract translation: 静电放电ESD保护电路装置可连接到电子电路的第一引脚和第二引脚，并布置成至少部分地吸收通过第一引脚或第二引脚中的至少一个进入电子电路的ESD电流 ESD应力事件。 保护电路装置包括第一ESD保护电路，其布置成在ESD应力事件的第一部分期间吸收ESD电流的第一部分，在第一部分期间ESD电流的电平超过预定电流阈值; 以及第二ESD保护电路，其布置成吸收ESD电流的第二部分，所述第二部分具有低于电流阈值的电流水平，至少在ESD应力事件的第二部分期间。 第二ESD保护电路包括限流电路，其被布置为将通过第二ESD保护电路的至少一部分的电流限制到电流阈值。

公开(公告)号：US09437574B2

公开(公告)日：2016-09-06

申请号：US14042662

申请日：2013-09-30

Applicant: Tu-Anh N. Tran ,  Chu-Chung Lee

Inventor： Tu-Anh N. Tran ,  Chu-Chung Lee

IPC: H05K1/11 ,  H05K1/09 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/8581 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  Y10T29/49124 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01012 ,  H01L2924/01016 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.

Abstract translation: 电子部件封装包括基板和电介质结构。 电介质结构包括具有突出部分和下部分的顶表面。 突出部位于大于下部的第二高度的第一高度。 导电接合焊盘位于电介质结构之上。 球接合电耦合接合焊盘和接合线。 位于球焊接和焊盘之间的金属间化合物由球焊和焊盘的材料形成，并将焊接焊盘电连接到球焊上。 接合焊盘的一部分垂直地位于电介质结构的顶表面的下部的一部分和金属间化合物之间。 接合焊盘的没有部分垂直地位于突出部分的至少一部分和金属间化合物之间。

公开(公告)号：US09436846B2

公开(公告)日：2016-09-06

申请号：US14401149

申请日：2012-05-30

Applicant: David H. Hartley ,  Elkana Korem

Inventor： David H. Hartley ,  Elkana Korem

IPC: G06F21/71 ,  G06F21/62 ,  G06F21/79 ,  G06F21/72 ,  G06F13/16 ,  G06F21/57 ,  G09C1/00 ,  H04L9/08 ,  H04N21/426 ,  H04N21/443 ,  H04N21/462 ,  H04N21/4405

CPC classification number: G06F21/71 ,  G06F21/575 ,  G06F21/62 ,  G06F21/72 ,  G06F21/79 ,  G09C1/00 ,  H04L9/0822 ,  H04L9/0894 ,  H04L2209/12 ,  H04N21/42646 ,  H04N21/42692 ,  H04N21/4405 ,  H04N21/4432 ,  H04N21/4435 ,  H04N21/462

Abstract: A semiconductor device having a plurality of on-chip processors, a plurality of key RAMs, a plurality of key RAM controllers, a fuse bank, a fuse bank controller and a boot controller is described. The boot controller is arranged to, in a first programming stage, allocate a first array of fuses in the fuse bank in dependence on the size of a first device key for storing the first device key in the fuse bank and, during boot-time, provide the first device key to a first key RAM controller. The fuse bank controller is arranged to program the first array of fuses with the first device key in the first programming stage, provide the first device key to the boot controller during boot-time, and prevent access to the first device key in the fuse bank during run-time. The first key RAM controller is arranged to, during boot-time, store the first device key in the first key RAM, and, during run-time, restrict access to the first device key in the first key RAM to exclusive access by the first on-chip processor. The first on-chip processor is arranged to, during run-time, retrieve the first device key from the first key RAM (110) and use the first device key in the first key-protected processing.

Abstract translation: 描述了具有多个片上处理器，多个键RAM，多个键RAM控制器，熔丝组，熔丝组控制器和引导控制器的半导体器件。 引导控制器被布置为在第一编程阶段中，根据用于将第一设备密钥存储在熔丝组中的第一设备密钥的大小，在熔丝组中分配熔丝的第一阵列，并且在引导时间期间， 向第一个键RAM控制器提供第一个设备密钥。 保险丝组控制器被布置为在第一编程阶段用第一设备密钥对第一阵列熔丝进行编程，在引导期间向引导控制器提供第一设备密钥，并且防止访问熔丝库中的第一设备密钥 在运行期间。 第一钥匙RAM控制器被布置成在引导期间将第一设备密钥存储在第一密钥RAM中，并且在运行时间期间限制访问第一密钥RAM中的第一设备密钥以由第一密钥RAM独占访问 片上处理器。 第一片上处理器被布置为在运行时期间从第一密钥RAM（110）检索第一设备密钥，并且在第一密钥保护处理中使用第一设备密钥。

公开(公告)号：US09436546B2

公开(公告)日：2016-09-06

申请号：US14258327

申请日：2014-04-22

Applicant: Ray Marshall ,  Joseph Charles Circello ,  Wilhard Christophorus Von Wendorff

Inventor： Ray Marshall ,  Joseph Charles Circello ,  Wilhard Christophorus Von Wendorff

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1048

Abstract: The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Abstract translation: 本发明涉及一种用于在总线控制器（例如CPU）和存储器控制器之间传送数据元素的装置。 地址转换器被安排为从CPU接收写入地址，修改写入地址并将修改的写入地址发送到存储器控制器。 ECC计算器被布置成从CPU接收与写入地址相关联的写入输入数据，并且基于写入输入数据生成纠错码。 串联器被配置为从CPU接收写入输入数据，并从ECC计算器接收纠错码，并且连接写入输入数据和纠错码以获得写入输出数据，并发送写入输出 数据到存储器控制器。

公开(公告)号：US09435862B2

公开(公告)日：2016-09-06

申请号：US14330544

申请日：2014-07-14

Applicant: Vladimir Litovchenko ,  Heiko Ahrens ,  Andreas Roland Stahl

Inventor： Vladimir Litovchenko ,  Heiko Ahrens ,  Andreas Roland Stahl

IPC: G01R31/28 ,  G01R31/3187 ,  G01R31/317

CPC classification number: G01R31/3187 ,  G01R31/31721 ,  G01R31/31727

Abstract: An integrated circuit device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication of at least one power dissipation parameter for at least a part of the IC device, and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device.

Abstract translation: 一种集成电路装置，包括至少一个自检部件，被布置成在IC器件的自检执行阶段期间在至少一个自检结构内执行自检，以及至少一个时钟控制部件，被布置成至少提供 至少在IC器件的自检执行阶段期间至少一个自检部件的一个时钟信号。 所述至少一个时钟控制部件还被布置成接收至少一个IC器件的至少一部分功率耗散参数的指示，并且调制提供给所述至少一个自检的至少一个时钟信号 至少部分地基于所述IC器件的至少一部分的所接收的至少一个功耗参数。

公开(公告)号：US09429966B2

公开(公告)日：2016-08-30

申请号：US13979860

申请日：2011-01-31

Applicant: Michael Priel ,  Dan Kuzmin ,  Anton Rozen

Inventor： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC: G05F1/46 ,  G11C5/14

CPC classification number: G05F1/462 ,  G11C5/147 ,  G11C7/04 ,  G11C16/30

Abstract: An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.

Abstract translation: 提供一种集成电路（IC）装置，其包括至少一个内部电压调节器，其布置成在其第一输入处接收电压供应信号，在其第二输入处接收控制信号，根据 接收到的控制信号，并在其输出端提供稳压电压信号。 IC器件还包括至少一个电压调节功率控制模块，其可操作地耦合到所述至少一个内部电压调节器的第二输入端并被布置成向其提供控制信号。 电压调节功率控制模块还被布置成接收至少一个IC器件条件指示，并且至少部分地基于对应于所述at的IC器件的可用热功率预算来生成用于所述至少一个内部稳压器的控制信号 至少一个IC器件条件指示。

公开(公告)号：US20160246358A1

公开(公告)日：2016-08-25

申请号：US15024443

申请日：2013-09-27

Applicant: Eran GLICKMAN ,  Ron BAR ,  Benny MICHALOVICH

Inventor： ERAN GLICKMAN ,  RON BAR ,  BENNY MICHALOVICH

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  G06F1/3253 ,  G06F13/40 ,  G06F2213/0038 ,  Y02D10/151

Abstract: A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2). The layered network (10; 11; 12) further includes a powering controller (25) configured to, during offload of the data, put a particular network element (Ei2) of the second set (S2) at the second layer (L2) in an on state only if at least a particular network element (Ei1) of the particular subset (S1) of the network elements of the first set (S1) at the first layer (L1) is in an on state and at least one of the network elements of the first set (S1) is in an off state. The powering controller (25) is configured to discriminate between chains of network elements formed by at least network elements of the first set (S1) and network elements of the second set (S2) and to have a chain in an on state if a first network element of the chain at a highest layer hierarchy is in an on state.

Abstract translation: 分层网络（10; 11; 12），用于在通信处理器（100; 110; 120）中提供数据的卸载。 分层网络（10; 11; 12）包括第一层（L1）处的网络单元的第一组（S1）和第二层（L2）处的一个或多个网络单元的第二组（S2）。 第一组（S1）的网元被配置为处理输入数据，并且第二层（L2）处的一个或多个网络元件的第二组（S2）的网络元件被配置为处理从第一组 设置（S1）网元。 网络单元的第一组（Si1）的网元的特定子集（Si1）的网元仅连接到第二组（S2）的特定网元（Ei2），以传送由第 特定子集（Si1）到第二集合（S2）的特定网络元素（Ei2）的网络元素。 分层网络（10; 11; 12）还包括供电控制器（25），其配置为在卸载数据期间将第二组（S2）的特定网元（Ei2）放置在第二层（L2）处 只有在第一层（L1）处的第一组（S1）的网络元件的特定子集（S1）的至少特定网元（Ei1）处于开状态并且至少一个 第一组（S1）的网元处于关闭状态。 供电控制器（25）被配置为区分由至少第一组（S1）的网络元件和第二组（S2）的网络元件形成的网络元件链，并且如果第一 在最高层层次上的链的网元处于开状态。

公开(公告)号：US09425115B2

公开(公告)日：2016-08-23

申请号：US14104658

申请日：2013-12-12

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Ruben B. Montez ,  Robert F. Steimle

IPC: H01L23/10 ,  H01L23/04 ,  H01L21/74 ,  H01L23/00

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L21/743 ,  H01L23/04 ,  H01L23/053 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16788 ,  H01L2924/00

Abstract: A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

Abstract translation: 一种键合半导体器件，包括支撑衬底，相对于所述支撑衬底的一侧定位的半导体器件，覆盖所述支撑衬底和所述器件的帽衬底，所述支撑衬底和所述帽衬底之间的玻璃料接合环，电 支撑基板和盖基板之间的导电环。 导电环在半导体器件周围形成内环，并且玻璃料接合环在半导体器件周围形成外部结合环。

公开(公告)号：US09424379B2

公开(公告)日：2016-08-23

申请号：US14398901

申请日：2012-05-31

Applicant: Xavier Hours ,  Pascal Caunegre ,  Christophe Oger ,  Mehul Shroff

Inventor： Xavier Hours ,  Pascal Caunegre ,  Christophe Oger ,  Mehul Shroff

IPC: G06F9/455 ,  G06F17/50 ,  G06F11/22 ,  G06F11/26

CPC classification number: G06F17/5009 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5081

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation. The simulation system further comprises a reporting unit for preparing a report of the rule scores associated with the one or more violation rules and for reporting the report to a user. A method of testing a simulation of a device against one or more violation rules is described.

Abstract translation: 描述了用于针对一个或多个违规规则来测试设备的模拟的仿真系统。 该仿真系统包括：用于使用设备设计，设备模型和仿真场景执行设备的仿真的设备模拟器; 和一个或多个违规监视器，每个违规规则一个。 每个违规监视器包括违反信息检测器，用于在执行模拟期间检测一个或多个违反相应违规规则的违规，并且对于每个违规，确定表示相应违规的信息; 侵权分数单元，用于针对每个违反相应的违规规则的违反分数，根据表示违规的信息和违规规则特定方案来计算违规分数，以及规则评分单元，用于根据相应的违规规则， 来自模拟期间一次或多次违规的违规分数的规则得分。 所述模拟系统还包括报告单元，用于准备与所述一个或多个违规规则相关联的所述规则得分的报告，以及用于向所述用户报告所述报告。 描述了针对一个或多个违规规则来测试设备的仿真的方法。

公开(公告)号：US09424200B2

公开(公告)日：2016-08-23

申请号：US13842516

申请日：2013-03-15

Applicant: Thomas E. Tkacik ,  Matthew W. Brocker ,  Carlin R. Covey

Inventor： Thomas E. Tkacik ,  Matthew W. Brocker ,  Carlin R. Covey

IPC: G06F12/00 ,  G06F12/10 ,  G06F21/57 ,  G06F21/64

CPC classification number: G06F12/1009 ,  G06F21/57 ,  G06F21/64

Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.

Abstract translation: 提供与具有存储器的运行时完整性检查（RTIC）方法兼容，该存储器具有至少部分存储随时间改变的数据或至少部分被配置为虚拟存储器的数据。 例如，该方法可以包括通过作为示例的操作系统存储页面条目表和访问页面条目，或者作为另一示例，管理程序来在存储器上执行RTIC，其中作为示例，例如， 操作系统，作为另一示例，管理程序，或者作为另一示例存储应用软件。 该表可以例如存储在安全存储器或外部存储器中。 页面条目包括页面的哈希值和指示哈希值的有效性状态的散列有效指示符。 页面条目还可以包括指示存储器页面的驻留状态的驻留指示符。