Calibration of voltage controlled oscillators
    61.
    发明授权
    Calibration of voltage controlled oscillators 有权
    压控振荡器的校准

    公开(公告)号:US07728679B2

    公开(公告)日:2010-06-01

    申请号:US12171277

    申请日:2008-07-10

    CPC classification number: H03L7/099

    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

    Abstract translation: 一种用于校准VCO(10,40)的偏置电流以最小化相位噪声的校准电路(20,50)和方法(60)。 校准电路(20,50)在偏置电流超过预定范围的同时监视VCO(10,40)的共模节点处的平均电压。 校准电路(20,50)识别与最小平均共模电压相关联的偏置电流,并利用该偏置电流来校准VCO(10,40)的偏置晶体管。

    Noise alarm timer function for three-axis low frequency transponder
    62.
    发明授权
    Noise alarm timer function for three-axis low frequency transponder 有权
    三轴低频转发器的噪声报警定时器功能

    公开(公告)号:US07209030B2

    公开(公告)日:2007-04-24

    申请号:US11079787

    申请日:2005-03-14

    CPC classification number: B60R25/24 B60R25/406 G07C9/00309 G07C2009/00769

    Abstract: A remote keyless entry (RKE) transponder has a noise alarm timer having a time interval used for determining whether a received signal meets a predefined condition within a time interval. If the received signal meets the predefined condition within the time interval, the noise alarm timer is disabled and the RKE transponder circuits are enabled so that normal operation in processing the desired signal commences. If the received signal does not meet the predefined condition within the time interval the noise alarm timer issues an alert signal, whereby appropriate action may be taken such as adjusting the channel input sensitivity, disabling a channel, or placing the RKE transponder into a sleep mode in order to reduce the power consumption caused by undesired input signals. A smart wake-up filter determines whether or not the input signal meets the predefined condition within the time interval.

    Abstract translation: 远程无钥匙进入(RKE)转发器具有噪声报警定时器,其具有用于确定接收到的信号是否在时间间隔内满足预定义条件的时间间隔。 如果接收到的信号在时间间隔内满足预定义的条件,噪声警报定时器被禁止,并且RKE应答器电路被使能,使得处理所需信号的正常操作开始。 如果接收到的信号在时间间隔内不满足预定义的条件,则噪声报警定时器发出报警信号,由此可以采取适当的动作,例如调整通道输入灵敏度,禁用通道或将RKE应答器置于睡眠模式 以减少由不期望的输入信号引起的功耗。 智能唤醒滤波器确定输入信号是否在时间间隔内满足预定义的条件。

    Microcontroller instruction set
    63.
    发明授权
    Microcontroller instruction set 有权
    微控制器指令集

    公开(公告)号:US07206924B2

    公开(公告)日:2007-04-17

    申请号:US10751210

    申请日:2003-12-31

    Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

    Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器,包括程序计数器(PC)和工作寄存器(W),映射到数据存储器中。 正交(对称)指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此,在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据,而不经过W寄存器。 从而增加性能并减少程序内存的使用。

    Secure self learning system
    64.
    发明授权
    Secure self learning system 失效
    安全自学系统

    公开(公告)号:US6166650A

    公开(公告)日:2000-12-26

    申请号:US868131

    申请日:1997-06-03

    Inventor: Frederick Bruwer

    Abstract: A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder and a decoder, the encoder encoding variable information including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.

    Abstract translation: 一种用于远程控制具有安全自学能力的装置的方法和系统。 该系统包括编码器和解码器,编码器编码包括使用非线性算法的用户密钥的变量信息以产生传输到解码器的编码值,解码器使用相同的算法解码该值。 在学习模式下,将新的编码器添加到系统中。 新编码器使用密钥生成种子生成编码值。 解码器在接收到编码的密钥生成种子后,基于解码的密钥生成种子产生解码密钥。 解码密钥存储在解码器存储器中,从而以安全的方式有效地识别新的编码器。

    Security for digital signal processor program memory
    65.
    发明授权
    Security for digital signal processor program memory 失效
    数字信号处理器程序存储器的安全性

    公开(公告)号:US5014191A

    公开(公告)日:1991-05-07

    申请号:US189189

    申请日:1988-05-02

    CPC classification number: G06F21/79 G06F21/74 G06F2221/2105

    Abstract: The processor executes programs from an internal EEPROM or from an external source. The EEPROM can be read either by a special operating (test) mode of the processor or by an instruction executing under normal operating mode from the EEPROM or from an external source. Similarly, the EEPROM can be programmed (written) either by a special operating mode or by under a normal operating mode instruction. The read and write circuits for the EEPROM are controlled to provide two levels of security against piracy of programmed information. In the first level, access is prevented for the read and write test modes and also for the read and write normal operating instructions if the instructions originate from an external source. In the second level, program execution from external source is also disabled.

    Abstract translation: 处理器从内部EEPROM或外部源执行程序。 EEPROM可以通过处理器的特殊操作(测试)模式或通过从EEPROM或外部源在正常工作模式下执行的指令来读取。 类似地,EEPROM可以通过特殊操作模式或正常工作模式指令进行编程(写入)。 控制EEPROM的读和写电路,以提供两级安全性,防止编程信息的盗版。 在第一级中,如果指令源于外部源,则可以访问读取和写入测试模式以及读取和写入正常操作指令。 在第二级,外部源程序执行也被禁用。

    Regression neural network for identifying threshold voltages to be used in reads of flash memory devices

    公开(公告)号:US12175363B2

    公开(公告)日:2024-12-24

    申请号:US17089891

    申请日:2020-11-05

    Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

    Method and apparatus for decoding with trapped-block management

    公开(公告)号:US11843393B2

    公开(公告)日:2023-12-12

    申请号:US17952240

    申请日:2022-09-24

    CPC classification number: H03M13/1111 H03M13/611

    Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

    Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames

    公开(公告)号:US20230300047A1

    公开(公告)日:2023-09-21

    申请号:US18202899

    申请日:2023-05-27

    CPC classification number: H04L43/062 H04L43/0894

    Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

Patent Agency Ranking