公开(公告)号：US08502329B2

公开(公告)日：2013-08-06

申请号：US13224297

申请日：2011-09-01

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L29/84

CPC classification number: B81C1/00698 ,  B81C1/00682 ,  H01G5/18 ,  H04R19/005 ,  H04R19/04

Abstract: A MEMS device includes a substrate. The substrate has a plurality of through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm.

Abstract translation: MEMS器件包括衬底。 衬底在膜片区域内的衬底中具有多个通孔，并且可选地在隔膜区域处具有与第二表面相邻的凹陷空间。 然后，第一介电结构层从第一表面设置在衬底上，其中第一介电结构层具有对应于通孔的多个开口，其中每个通孔保持被第一介电结构层暴露。 具有腔室的第二电介质结构层设置在第一介电结构层上，其中腔室暴露第一介电结构层的开口和衬底的通孔以连接到凹陷空间。 MEMS隔膜嵌入在腔室上方的第二电介质结构层中，其中在衬底和MEMS隔膜之间形成气隙。

公开(公告)号：US20110302355A1

公开(公告)日：2011-12-08

申请号：US12793701

申请日：2010-06-04

Applicant: Gene Lin

Inventor： Gene Lin

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: The invention is directed to a mapping method in a memory device with a plurality of memory chips in a sequence of 0 to K, K≧1. Each of the memory chips has a plurality of data blocks. The mapping method includes setting a block sequence number “(K+1)*n” to the (n+1)th data block of the memory chip K, wherein n is a positive integer greater than or equal to 0. Based on the mapping method, a writing method is also provided.

Abstract translation: 本发明涉及具有多个存储器芯片的存储器件中的映射方法，该存储器芯片的序列为0至K，K≥1。 每个存储器芯片具有多个数据块。 映射方法包括将块序列号“（K + 1）* n”设置到存储芯片K的第（n + 1）个数据块，其中n是大于或等于0的正整数。基于 映射方法，还提供了一种写入方法。

公开(公告)号：US20110183456A1

公开(公告)日：2011-07-28

申请号：US12691754

申请日：2010-01-22

Applicant: Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L21/302

CPC classification number: B81C1/00246 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2201/016 ,  B81C2203/0714 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: A method for fabricating MEMS device includes: providing a single crystal substrate, having first surface and second surface and having a MEMS region and an IC region; forming SCS mass blocks on the first surface in the MEMS region; forming a structural dielectric layer over the first surface of the substrate, wherein a dielectric member of the structural dielectric layer is filled in spaces surrounding the SCS mass blocks in the MEMS region, the IC region has a circuit structure with an interconnection structure formed in the structural dielectric layer; patterning the single crystal substrate by an etching process on the second surface to expose a portion of the dielectric member filled in the spaces surrounding the SCS mass blocks; performing isotropic etching process at least on the dielectric portion filled in the spaces surrounding the SCS mass blocks. The SCS mass blocks are exposed to release a MEMS structure.

Abstract translation: 一种制造MEMS器件的方法包括：提供具有第一表面和第二表面并具有MEMS区域和IC区域的单晶衬底; 在MEMS区域的第一表面上形成SCS质量块; 在所述基板的所述第一表面上形成结构介电层，其中所述结构介电层的电介质部件填充在所述MEMS区域中围绕所述SCS质量块的空间中，所述IC区域具有形成在所述MEMS区域中的互连结构的电路结构 结构介电层; 通过在第二表面上的蚀刻工艺对单晶衬底进行图案化，以暴露填充在围绕SCS质量块的空间中的电介质构件的一部分; 至少在填充在SCS质量块周围的空间中的电介质部分上进行各向同性蚀刻处理。 暴露SCS质量块以释放MEMS结构。

公开(公告)号：US20110156106A1

公开(公告)日：2011-06-30

申请号：US12647559

申请日：2009-12-28

Applicant: Chien-Hsing Lee ,  Tsung-Min Hsieh ,  Jhyy-Cheng Liou

Inventor： Chien-Hsing Lee ,  Tsung-Min Hsieh ,  Jhyy-Cheng Liou

IPC: H01L29/84 ,  H01L27/092 ,  H01L23/00

CPC classification number: B81C1/00246 ,  B81B7/0064 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81C2203/0714 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space.

Abstract translation: 密封微机电系统（MEMS）封装包括CMOS MEMS芯片和第二基板。 CMOS MEMS芯片具有第一衬底，结构介电层，CMOS电路和MEMS结构。 结构介电层设置在第一结构基板的第一侧上。 结构介电层具有用于电互连的互连结构，并且还具有保护结构层。 第一结构基底具有至少一个孔。 该孔位于保护结构层之下，以形成至少一个腔室。 该室暴露于第一结构基板的第二侧的环境。 该腔室还包括MEMS结构。 第二衬底在室上粘附到第一衬底的第二侧以形成密封空间，并且MEMS结构在空间内。

公开(公告)号：US20100072561A1

公开(公告)日：2010-03-25

申请号：US12235549

申请日：2008-09-22

Applicant: Chien-Hsing Lee ,  Tsung-Min Hsieh

Inventor： Chien-Hsing Lee ,  Tsung-Min Hsieh

IPC: H01L29/84 ,  H01L21/311 ,  H01L21/00

CPC classification number: B81C1/00246 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00182 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01L29/84 ,  H04R19/005 ,  H04R19/04 ,  H04R31/003

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, having a first side and second side, the second side has a cavity and a plurality of venting holes in the substrate at the second side with connection to the cavity. However, the cavity is included in option without absolute need. A structural dielectric layer has a dielectric structure and a conductive structure in the dielectric structure. The structural dielectric layer has a chamber in connection to the cavity by the venting holes. A suspension structure layer is formed above the chamber. An end portion is formed in the structural dielectric layer in fix position. A diaphragm has a first portion of the diaphragm fixed on the suspension structure layer while a second portion of the diaphragm is free without being fixed.

Abstract translation: 微电子机械系统（MEMS）装置包括具有第一侧和第二侧的基板，第二侧在第二侧具有空腔和多个通孔，第二侧具有连接到空腔的多个通气孔。 然而，空腔被包括在选项中，绝对不需要。 结构介电层在电介质结构中具有介电结构和导电结构。 结构介电层具有通过排气孔连接到空腔的腔室。 在室上形成悬浮结构层。 在固定位置的结构介电层中形成端部。 隔膜具有固定在悬架结构层上的隔膜的第一部分，而隔膜的第二部分是自由的而不固定。

公开(公告)号：US20090179233A1

公开(公告)日：2009-07-16

申请号：US12014810

申请日：2008-01-16

Applicant: Chien-Hsing Lee ,  Tsung-Min Hsieh

Inventor： Chien-Hsing Lee ,  Tsung-Min Hsieh

IPC: H01L21/50 ,  H01L29/66

CPC classification number: B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges.

Abstract translation: 本发明提供了一种MEMS器件，可在许多MEMS器件上实现，例如MEMS麦克风，MEMS扬声器，MEMS加速度计，MEMS陀螺仪。 MEMS器件包括衬底。 电介质结构层设置在衬底上，其中电介质结构层具有露出衬底的开口。 隔膜层设置在电介质结构层上，其中隔膜层覆盖电介质结构层的开口以形成室。 导电电极结构适用于隔膜层和基板以存储非易失性电荷。

公开(公告)号：US20090132770A1

公开(公告)日：2009-05-21

申请号：US11943228

申请日：2007-11-20

Applicant: Yen-Chin Lin

Inventor： Yen-Chin Lin

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0886 ,  G06F2212/2022

Abstract: The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.

Abstract translation: 本发明提供一种插入在主机和闪速存储器之间的数据高速缓存架构，所述数据高速缓存架构包括：缓冲存储器，从所述主机接收数据; 存储器控制器，将数据部署在缓冲存储器中; 以及由存储器控制器根据高速缓存算法控制的数据高速缓冲存储器。 可以使用数据高速缓存架构中使用的数据高速缓存结构和缓存算法来最小化NAND型闪存设备的编程/擦除计数。

公开(公告)号：US07233527B2

公开(公告)日：2007-06-19

申请号：US11162730

申请日：2005-09-21

Applicant: Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/3468

Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

公开(公告)号：US07161850B2

公开(公告)日：2007-01-09

申请号：US11292347

申请日：2005-12-02

Applicant: Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

IPC: G11C7/10

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US07085160B2

公开(公告)日：2006-08-01

申请号：US10958331

申请日：2004-10-06

Applicant: Hitoshi Shiga ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chin Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。