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123 条记录 (耗时 0.02 秒)

    Supporting speculative modification in a data cache
    63.
    发明授权
    Supporting speculative modification in a data cache 有权
    支持数据缓存中的推测性修改

    公开(公告)号：US07873793B1

    公开(公告)日：2011-01-18

    申请号：US11807629

    申请日：2007-05-29

    申请人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

    发明人： Guillermo Rozas ,  Alexander Klaiber ,  David Dunn ,  Paul Serris ,  Lacky Shah

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/603

    摘要： Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.

    摘要翻译： 提供和描述了用于支持数据高速缓存中的推测性修改的方法和系统。 数据高速缓存包括多条高速缓存行。 每个高速缓存线包括用于指示多个状态中的任何一个的状态指示符，其中，所述多个状态包括能够跟踪对相应高速缓存线中的数据的推测性修改的推测状态。 响应于在推测性执行指令期间到达特定指令边界时执行的第一操作，推测状态使得对相应高速缓存行中的数据进行推测性修改是永久性的。 此外，推测状态使得能够响应于在推测性执行指令期间不能达到特定指令边界时执行的第二操作来撤消对相应高速缓存行中的数据的推测性修改。

    INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECT
    64.
    发明公开
    INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECT 审中-公开

    公开(公告)号：US20240338329A1

    公开(公告)日：2024-10-10

    申请号：US18747410

    申请日：2024-06-18

    申请人： SiFive, Inc.

    发明人： Robert P. Adler ,  David Parry ,  Rick H. Y. Chen ,  Henry Cook

    IPC分类号： G06F13/16 ,  G06F12/0888

    CPC分类号： G06F13/1668 ,  G06F12/0888 ,  G06F2212/603

    摘要： Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.

    WRITE DATA CACHE METHOD AND SYSTEM, DEVICE, AND STORAGE MEDIUM
    65.
    发明公开
    WRITE DATA CACHE METHOD AND SYSTEM, DEVICE, AND STORAGE MEDIUM 审中-公开

    公开(公告)号：US20240264940A1

    公开(公告)日：2024-08-08

    申请号：US18565053

    申请日：2022-05-26

    申请人： SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.

    发明人： Jiang WANG ,  Shuqing LI ,  Huajin SUN

    IPC分类号： G06F12/0804

    CPC分类号： G06F12/0804 ,  G06F2212/603

    摘要： A method and system for high-speed caching of data writing, a device and a storage medium. The method includes: in response to receiving a data-writing operating instruction emitted by a host, creating a controlling page table and filling sequentially a plurality of control blocks into the controlling page table; submitting an entry pointer of a first instance of the control blocks to a work-queue scheduling engine, to execute tasks corresponding to the plurality of control blocks alternately in the work-queue scheduling engine; sending in advance a completion response to the host and notifying a firmware to perform subsequent processing and falling-into-disk of data; and in response to ending of execution of a task corresponding to a last one instance of the control blocks, releasing a used resource of the controlling page table.

    Determining whether to perform an additional lookup of tracking circuitry
    68.
    发明授权
    Determining whether to perform an additional lookup of tracking circuitry 有权

    公开(公告)号：US11907130B1

    公开(公告)日：2024-02-20

    申请号：US18101602

    申请日：2023-01-26

    申请人： Arm Limited

    发明人： Alexander Alfred Hornung ,  Kenny Ju Min Yeoh

    IPC分类号： G06F12/0877 ,  G06F9/38 ,  G06F12/0864

    CPC分类号： G06F12/0877 ,  G06F9/3834 ,  G06F12/0864 ,  G06F2212/603 ,  G06F2212/6022

    摘要： An apparatus comprising a cache comprising a plurality of cache entries, cache access circuitry responsive to a cache access request to perform, based on a target memory address associated with the cache access request, a cache lookup operation, tracking circuitry to track pending requests to modify cache entries of the cache, and prediction circuitry responsive to the cache access request to make a prediction of whether the pending requests tracked by the tracking circuitry include a pending request to modify a cache entry associated with the target memory address, wherein the cache access circuitry is responsive to the cache access request to determine, based on the prediction, whether to perform an additional lookup of the tracking circuitry. A method and a non-transitory computer-readable medium to store computer-readable code for fabrication of the apparatus are also provided.