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    A Low Power SRAM Bitcell Using Resonant Drive Circuitry
    63.
    发明申请
    A Low Power SRAM Bitcell Using Resonant Drive Circuitry 审中-公开

    公开(公告)号：US20180218768A1

    公开(公告)日：2018-08-02

    申请号：US15746615

    申请日：2016-07-26

    Applicant: Power Down Semiconductor Inc.

    Inventor： David A. Huffman

    IPC: G11C11/419 ,  G11C7/12 ,  H01L27/11 ,  G11C7/06

    CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C7/12 ,  G11C11/412 ,  H01L27/11

    Abstract: An SRAM cell comprises a first inverter having an output lead coupled to the input lead of a second inverter via a first resistor. The output lead of the second inverter is coupled to the first inverter input lead via a second resistor. A first write bit line is coupled to the first inverter input lead via a first switch, and a second write bit line is coupled to the second inverter input lead via a second switch. Because of the resistors, the circuitry driving write bit lines does not have to overpower the inverters when writing data to the cell. The cell is part of an array comprising several columns of SRAM cells, each column coupled to a pair of write bit lines. A resonating oscillator drives the write bit lines with a sine wave. This reduces the power consumed by the SRAM array.

    Sense amplifier in low power and high performance SRAM
    67.
    发明授权
    Sense amplifier in low power and high performance SRAM 有权

    公开(公告)号：US10008261B2

    公开(公告)日：2018-06-26

    申请号：US15706901

    申请日：2017-09-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Vinod Menezes

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C5/14 ,  G11C11/413

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/065 ,  G11C11/412 ,  G11C11/413

    Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.

    STATIC RANDOM ACCESS MEMORY CELL
    68.
    发明申请
    STATIC RANDOM ACCESS MEMORY CELL 审中-公开

    公开(公告)号：US20180174642A1

    公开(公告)日：2018-06-21

    申请号：US15851531

    申请日：2017-12-21

    Applicant: IMEC VZW ,  Vrije Universiteit Brussel

    Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

    IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

    CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

    Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

    SRAM cell structure
    69.
    发明授权
    SRAM cell structure 有权

    公开(公告)号：US09991268B1

    公开(公告)日：2018-06-05

    申请号：US15617219

    申请日：2017-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jhon-Jhy Liaw

    IPC: H01L27/00 ,  H01L27/11 ,  H01L29/423 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/51 ,  G11C11/412

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42372 ,  H01L29/517 ,  H01L29/518

    Abstract: A static random access memory (SRAM) cell and a SRAM cell structure are provided. The SRAM cell includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first conductive line pattern and a second conductive line pattern. A first gate electrode pattern of the first pull-down transistor and a second gate electrode pattern of the first pull-up transistor are physically separated from each other and electrically connected to the first conductive line pattern. The second inverter includes a second pull-down transistor, a second pull-up transistor and a second conductive line pattern. A third gate electrode pattern of the second pull-down transistor and a fourth gate electrode pattern of the second pull-up transistor are physically separated from each other and electrically connected to the second conductive line pattern.

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