公开(公告)号：US12075627B2

公开(公告)日：2024-08-27

申请号：US17412776

申请日：2021-08-26

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Alexander Reznicek ,  Wei Wang ,  Tao Li ,  Tsung-Sheng Kang

IPC: H10B61/00 ,  G11C11/15 ,  H10N50/01 ,  H10N50/85 ,  G11C11/00 ,  G11C13/00

CPC classification number: H10B61/00 ,  G11C11/15 ,  H10B61/10 ,  H10N50/01 ,  H10N50/85 ,  G11C11/005 ,  G11C13/0004

Abstract: An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.

公开(公告)号：US20240251571A1

公开(公告)日：2024-07-25

申请号：US18624983

申请日：2024-04-02

Applicant: SK hynix Inc.

Inventor： Hyung Keun KIM ,  Jun Ku AHN ,  Jun Young LIM ,  Sung Lae CHO

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/00 ,  H10N50/01 ,  H10N70/023 ,  H10N70/823 ,  H10B61/10 ,  H10B63/24

Abstract: A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

公开(公告)号：US20240251565A1

公开(公告)日：2024-07-25

申请号：US18600957

申请日：2024-03-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John P. LESSO ,  James T. DEAS

IPC: H10B61/00 ,  G06N3/02 ,  G11C11/16 ,  H10N50/10

CPC classification number: H10B61/10 ,  G06N3/02 ,  G11C11/165 ,  H10N50/10

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

公开(公告)号：US12048252B2

公开(公告)日：2024-07-23

申请号：US17959017

申请日：2022-10-03

Applicant: KIOXIA CORPORATION ,  SK HYNIX INC.

Inventor： Taiga Isoda ,  Eiji Kitagawa ,  Young Min Eeh ,  Tadaaki Oikawa ,  Kazuya Sawada ,  Kenichi Yoshino ,  Jong Koo Lim ,  Ku Youl Jung ,  Guk Cheon Kim

IPC: H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00

CPC classification number: H10N50/85 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3286 ,  H10B61/10 ,  H10B61/22

Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.

公开(公告)号：US20240237559A1

公开(公告)日：2024-07-11

申请号：US18345817

申请日：2023-06-30

Applicant: SK hynix Inc.

Inventor： Keo Rock CHOI ,  Cha Deok DONG

IPC: H10N70/00 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00

CPC classification number: H10N70/046 ,  H10B53/30 ,  H10B61/10 ,  H10B63/22 ,  H10N70/043 ,  H10N70/25

Abstract: A method for fabricating a selector may include: forming an insulating layer; doping the insulating layer with dopants by performing an ion implantation process; and performing a subsequent process to the insulating layer doped with the dopants for restoring damage caused by the ion implantation process.

公开(公告)号：US12035541B2

公开(公告)日：2024-07-09

申请号：US17462600

申请日：2021-08-31

Applicant: Kioxia Corporation

Inventor： Gu Tianyi

IPC: H10B63/00 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/24 ,  H10B61/10 ,  H10N70/231 ,  H10N70/8828

Abstract: A selector device includes: a first electrode; a second electrode; a selector layer that is disposed between the first electrode and the second electrode; and a stacked film that is disposed in at least one of a portion between the first electrode and the selector layer and a portion between the second electrode and the selector layer, and includes a first layer including at least one first element selected from the group consisting of carbon and metal and not including nitrogen and a second layer including nitride of the first element. The first layer is in contact with the selector layer.

公开(公告)号：US12002527B2

公开(公告)日：2024-06-04

申请号：US17584297

申请日：2022-01-25

Applicant: Attopsemi Technology Co., LTD

Inventor： Shine C. Chung

IPC: G11C17/18 ,  G11C11/16 ,  G11C17/16 ,  H10B20/20 ,  H10B61/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: G11C17/18 ,  G11C11/1659 ,  G11C17/16 ,  H10B20/20 ,  H10B61/10 ,  H10B63/00 ,  H10N70/231

Abstract: Programmable resistive memory can be integrated with wide-bandgap semiconductor devices on a wide-bandgap semiconductor, silicon, or insulator substrate. The wide-bandgap semiconductor can be group IV-IV, III-V, or II-VI crystal or compound semiconductor, such as silicon carbide or gallium nitride. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a metal, silicon, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. The selector in a programmable resistive memory can be a MOS or diode fabricated by wide-bandgap semiconductor.

公开(公告)号：US11991939B2

公开(公告)日：2024-05-21

申请号：US18079161

申请日：2022-12-12

Applicant: Kioxia Corporation

Inventor： Yoshinori Kumura

IPC: H10N70/00 ,  H10B61/00 ,  H01L29/36

CPC classification number: H10N70/8833 ,  H10B61/10 ,  H10N70/043 ,  H10N70/063 ,  H10N70/841 ,  H01L29/36

Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

公开(公告)号：US11985907B2

公开(公告)日：2024-05-14

申请号：US17202151

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Shogo Itai ,  Tadaomi Daibou ,  Yuichi Ito ,  Katsuyoshi Komatsu

IPC: H10N50/80 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10

CPC classification number: H10N50/80 ,  H01F10/3286 ,  H01F10/329 ,  H10B61/10 ,  H01F10/3254 ,  H01F10/3272 ,  H10N50/10

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

公开(公告)号：US11978491B2

公开(公告)日：2024-05-07

申请号：US17485129

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin ,  Raj Ramanujan

IPC: G11C11/16 ,  G06F11/10 ,  H01L25/065 ,  H10B61/00

CPC classification number: G11C11/1673 ,  G06F11/1068 ,  G11C11/161 ,  G11C11/1659 ,  H10B61/10 ,  H01L25/0657 ,  H01L2225/06562

Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.