公开(公告)号：US3865653A

公开(公告)日：1975-02-11

申请号：US43009774

申请日：1974-01-02

申请人： GOSER KARL

发明人： GOSER KARL

IPC分类号： G11C11/412 ,  H01L21/86 ,  H01L27/12 ,  H01L7/44

CPC分类号： H01L27/12 ,  G11C11/412 ,  H01L21/86 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/106

摘要： A logic circuit having a switching transistor and a load transistor constructed in accordance with complementary channel thin-film techniques wherein the switching transistor is produced by a double-diffusion process and the load transistor of the complementary type is produced during the process steps in the production of the switching transistor.

摘要翻译： 具有开关晶体管和负载晶体管的逻辑电路，所述开关晶体管和负载晶体管根据互补沟道薄膜技术构成，其中通过双扩散工艺制造开关晶体管，并且在生产过程中产生互补型负载晶体管 的开关晶体管。

公开(公告)号：US3860465A

公开(公告)日：1975-01-14

申请号：US32851573

申请日：1973-02-01

申请人： ERICSSON TELEFON AB L M

发明人： MATZNER EVA ,  STERNBECK OLAF

IPC分类号： H01L21/00 ,  H01L29/8605 ,  H01L7/50

CPC分类号： H01L29/8605 ,  H01L21/00 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/136

摘要： The invention refers to a method for obtaining an accurately determined high resistance in a resistor produced in a single crystalline substrate in the form of a diffused region limited in length, width and depth direction, which region is covered with an oxide layer and is provided with a first and a second window in the oxide layer for connection of two terminal contacts. According to the invention, a third window is made in the oxide layer on the top of the diffused region by means of a conventional photo-resist and etching technique whereupon the diffused region is etched in the depth direction through the third window for a predetermined time period during which such a quantity of material is removed that the resistance of the quantity of material remaining in the diffused region, measured between the first and second window, will be equal to a predetermined resistance value.

摘要翻译： 本发明涉及一种在长度，宽​​度和深度方向上限制的扩散区形式的单晶衬底中制造的电阻器中精确确定的高电阻的方法，该区域被氧化物层覆盖，并且具有 用于连接两个端子触点的氧化物层中的第一和第二窗口。 根据本发明，通过常规的光刻胶和蚀刻技术在扩散区域顶部的氧化物层中形成第三窗口，于是扩散区域沿深度方向通过第三窗口蚀刻预定时间 消除这样的材料量的时间段，即在第一和第二窗口之间测量的在扩散区域中剩余的材料的数量的电阻将等于预定的电阻值。

公开(公告)号：US3860461A

公开(公告)日：1975-01-14

申请号：US36498173

申请日：1973-05-29

申请人： TEXAS INSTRUMENTS INC

发明人： ROBINETTE JR WILLIAM C

IPC分类号： H01L21/306 ,  H01L21/00 ,  H01L21/22 ,  H01L23/29 ,  H01L7/44

CPC分类号： H01L21/00 ,  H01L23/29 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/106 ,  H01L2924/00

摘要： An improved method for selectively masking a substrate surface is disclosed. The method includes forming a first layer of a masking material on a substrate and patterning this layer to provide a plurality of accurately spaced apertures exposing corresponding spaced locations on the substrate surface. A second composite masking layer is formed over the structure and is patterned to provide a plurality of apertures exposing a first set of apertures in the first layer, thereby enabling modification of the characteristics of the set of substrate surface locations exposed through the corresponding apertures through the first and second layers. A third composite masking layer is then formed over the structure and patterned to expose a second set of apertures in the first layer, thereby enabling modification of the characteristics of a second set of substrate locations, while maintaining accurate spacing between substrate location.

摘要翻译： 公开了一种用于选择性掩蔽衬底表面的改进方法。 该方法包括在衬底上形成掩模材料的第一层并且图案化该层以提供暴露衬底表面上相应间隔位置的多个准确间隔的孔。 第二复合掩模层形成在该结构之上并且被图案化以提供暴露第一层中的第一组孔的多个孔，由此能够修改通过相应的孔暴露的一组衬底表面位置的特性 第一层和第二层。 然后在该结构上形成第三复合掩模层，并将其图案化以暴露第一层中的第二组孔，从而能够修改第二组衬底位置的特性，同时保持衬底位置之间的准确间隔。

公开(公告)号：US3847677A

公开(公告)日：1974-11-12

申请号：US32649373

申请日：1973-01-24

申请人： HITACHI LTD

发明人： TAKEDA T ,  NAKAZAWA Y ,  IKEDA H

IPC分类号： H01L21/00 ,  H01L21/761 ,  H01L7/54

CPC分类号： H01L21/761 ,  H01L21/00 ,  Y10S148/007 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S257/918

摘要： An improved process for the manufacture of a semiconductor device having a plurality of bipolar type semiconductor elements formed on a substrate and isolated from each other by diffusion layers. Each diffusion layer is formed by a diffusion layer diffused from an impurity source buried in the substrate into a semiconductor layer epitaxially grown on the substrate and another diffusion layer diffused from the surface of the epitaxially grown semiconductor layer until it is combined with the first-mentioned diffusion layer.

摘要翻译： 一种用于制造半导体器件的改进方法，该半导体器件具有形成在衬底上并通过扩散层彼此隔离的多个双极型半导体元件。 每个扩散层由扩散层形成，该扩散层从掩埋在衬底中的杂质源扩散到在衬底上外延生长的半导体层和从外延生长的半导体层的表面扩散的另一个扩散层，直到与前述 扩散层。

公开(公告)号：US3846198A

公开(公告)日：1974-11-05

申请号：US35632273

申请日：1973-05-02

申请人： RCA CORP

发明人： WEN C ,  CHIANG Y

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L23/36 ,  H01L27/00 ,  H01L7/50

CPC分类号： H01L24/26 ,  H01L21/00 ,  H01L23/36 ,  H01L24/83 ,  H01L27/00 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/135 ,  H01L2924/00

摘要： 1. A METHOD OF MAKING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: (A) FORMING ON A SURFACE OF A SUBRATE OF SINGLE CRYSTALLINE SILICON A THIN BARRIER LAYER OF SINGLE CRYSTALLINE P TYPE CONDUCTIVITY SILICON WITH THE FREE CARRIER CONCENTRATION BEING GREATER THAN 5 X 10**19 CM.-3, (B) FORMING ON SAID BARRIER LAYER A REGION OF SINGLE CRYSTALLINE SILICON, SAID REGION BEING OF A CONDUCTIVITY TYPE OR TYPES REQUIRED BY THE SEMICONDUCTOR DEVICE BEING FORMED, AND (C) REMOVING SAID SUBSTRATE BY ETCHING WITH A SOLUTION OF POTASSIUM HYDROXIDE AND 1-PROPANOL.

公开(公告)号：US3836446A

公开(公告)日：1974-09-17

申请号：US29059372

申请日：1972-09-20

申请人： RAYTHEON CO

发明人： TIEFERT K

IPC分类号： H01L21/00 ,  H01L21/3213 ,  H01L21/60 ,  H01L23/482 ,  C23B5/50 ,  C23C13/02 ,  C23C15/00

CPC分类号： H01L21/76897 ,  H01L21/00 ,  H01L21/32139 ,  H01L23/4822 ,  H01L24/01 ,  H01L2924/01029 ,  H01L2924/14 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/158 ,  H01L2924/00

摘要： SEMICONDUCTOR STRUCTURES HAVING MULTI-LAYER METAL CONDUCTORS FORMED ON THE SURFACE OF THE SEMICONDUCTOR DEVICES AND HAVING EXCESS METAL BETWEEN THE CONDUCTORS REMOVED BY SPUTTER ETCHING IN AN ATMOSPHERE WHICH PRODUCES OXIDATION OF ONE OF THE METAL LAYERS OF SAID CONDUCTORS. THE METAL COMPOUND MASK THUS FORMED INHIBITS THE ETCHING PROCESS IN THE REGIONS WHERE THE OIDIZED LAYER IS EXPOSED AND PROTECTS THE ACTIVE COMPONENTS BENEATH THE LAYER. THE OXIDIZED PORTIONS OF THE MASKING LAYER ARE THEN REMOVED BY A SUITABLE SOLVENT OR ETCH. A CHEMICAL ETCHING METAL COMPOUND MASK MAY BE FORMED OF A METAL AND THE SEMICONDUCTOR MATERIAL FOR SEPARATING THE CHIPS FROM THE WAFER BY ANISOTROPIC ETCHING.

公开(公告)号：US3834958A

公开(公告)日：1974-09-10

申请号：US9928970

申请日：1970-12-17

申请人： TEXAS INSTRUMENTS INC

发明人： BEAN K ,  GLEIM P

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/763 ,  H01L27/06 ,  H01L7/50

CPC分类号： H01L27/0652 ,  H01L21/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/122 ,  Y10S148/135 ,  Y10S148/15 ,  Y10S438/973

摘要： POLYCRYSTALLINE SILICON HAVING A NEEDLE-LIKE ORIENTED GRAIN STRUCTURE IS FOUND TO HAVE ANISOTROPIC ELECTRICAL AND THERMAL PROPERTIES. A MONOLITHIS INTEGRATED CIRCUIT STRUCTURE HAVING A PLURALITY OF MONOCRYSTALLINE SILICON ISLANDS IS FABRICATED IN A POLYCRYSTALLINE SILICON MATRIX HAVING SUCH A GRAIN STRUCTURE, WITH THE GRAIN DIRECTION ORIENTED TO PROVIDE MAXIMUM ELECTRICAL RESISTIVITY BETWEEN THE MONOCRYSATLLINE ISLANDS, AND MAXIMUM THERMAL CONDUCTIVITY TOWARD A HEADER OR OTHER HEAT SINK IN ONE EMBODIMENT, THE MONOCRYSTALLINE ISLANDS AND POLYCRYSTALLINE MATRIX ARE GROWN BY VAPOR DEPOSITION OF SILICON ON A MONOCRYSTALLINE SUBSTRATE PROVIDED WITH A SUITABLE MASKING PATTERN, WHEREBY THE POLYCRYSTALLINE MATERIAL GROWS ON THE MASK CONCURRENTLY WITH THE GROWTH OF MONOCRYSTALLINE SILICON ON THE UNMASKED AREAS OF THE SUBSTRATE.

公开(公告)号：US3826699A

公开(公告)日：1974-07-30

申请号：US35870173

申请日：1973-05-09

申请人： TOKYO SHIBAURA ELECTRIC CO

发明人： SAWAZAKI H ,  SUMITOMO Y ,  NIWA K ,  SAKAI K ,  TSUTSUMI H ,  INABA E

IPC分类号： H01L21/762 ,  H01L23/535 ,  H01L27/00 ,  H01L7/36 ,  H01L7/50 ,  H01L19/00

CPC分类号： H01L23/535 ,  H01L21/76297 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S438/977 ,  H01L2924/00

摘要： A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISES STEPS OF FORMING AN ENCLOSED GROOVE IN THE SURFCE OF A SEMICONDUCTOR WAFER, FORMING AN INNER DIELECTRIC LAYER ON THE SURFACE OF THE GROOVE, DEPOSITING AN EPITAXIAL LAYER ON SAID SURFACE OF THE WAFER AND THE SURFACE OF THE DIELECTRIC LAYER, FORMING AN OUTER DIELECTRIC LAYER ON THE EPITAXIAL LAYER, FORMING A SUPPORT SUBSTRATE ON THE OUTER DIELECTRIC LAYER, REMOVING THE WAFER IN A PREDETERMINED LEVEL TO FORM AN ISLAND REGION ENCLOSED BY THE OUTER DIELECTRIC LAYER AND FORMING A SEMICONDUTOR ELEMENT IN THE ISLAND REGION.

摘要翻译： 半导体集成电路包括形成在基板一侧的多个半导体元件。 半导体元件被盘形的外部电介质层包围，以与衬底绝缘，并且在其中包括与外部电介质层相邻的无底内部电介质层。 在由内层包围的区域中形成有PN结，其中周边位于其中。

公开(公告)号：US3826698A

公开(公告)日：1974-07-30

申请号：US28438172

申请日：1972-08-28

申请人： IBM

发明人： ANTIPOV I ,  MELZER P

IPC分类号： H01L21/8222 ,  H01L27/00 ,  H01L27/06 ,  H01L27/082 ,  H01L7/44

CPC分类号： H01L27/0826 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/0658 ,  Y10S148/03 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

摘要： A PROCESS FOR FORMING A PEDESTAL BASE TRANSISTOR IN WHICH A BURIED LAYER OF A FIRST CONDUCTIVITY TYPE IS DIFFUSED INTO A SUBSTRATE OF A SECOND CONDUCTIVITY TYPE. IMPURITIES OF THE SECOND CONDUCTIVITY TYPE, WHICH HAVE A HIGHER DIFFUSION RATE THAN THE DOPANT WHICH FORMS THE BURIED LAYER, ARE DIFFUSED INTO A LIMITED AREA OF THE BURIED LAYER. AN EPITAXIAL LAYER IS FORMED ON THE SURFACE OF THE SEMICONDUCTOR. DURING THE GROWTH OF THE EPITAXIAL LAYER, THE PREVIOUSLY DIFFUSED REGIONS OUTDIFFUSE INTO THE EPITAXIAL REGION. THE OUTDIFFUSION OF THE SECOND CONDUCTIVITY TYPE, DUE TO ITS FASTER DIFFUSING CHARACTERISTICS, APPROACHES THE SURFACE OF THEEPITAXIAL LAYER MORE CLOSELY THAN DOES THE BURIED LAYRE, THEREBY FORMING A PEDESTAL REGION. A SECOND DIFFUSION OF THE FAST DIFFUSING MATERIAL IS MADE THROUGH THE SURFACE OF THE EPITAXIAL LAYER AND CONTACTS THE PEDESTAL, THEREBY RESULLTING IN A HIGHLY DOPED PEDESR TAL TAL BASE REGION. DIFFUSED ISOLATION REGIONS AND AN EMITTER REGION ARE FORMED TO COMPLETE THE DIVICE IN MONOLITHIC FORM A METHOD FOR SIMULTANEOUSLY FORMING A SECOND TRANSISTOR OF THE COMPLEMENTARY TYPE TO THE FIRST TRANSISTOR USING THE SAME PROCESS STEPS IS ALSO DESCRIBED.

公开(公告)号：US3808475A

公开(公告)日：1974-04-30

申请号：US27044972

申请日：1972-07-10

申请人： AMDAHL CORP

发明人： BUELOW F ,  ZASIO J

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/522 ,  H01L27/04 ,  H01L27/118 ,  H01L19/00

CPC分类号： H01L27/11801 ,  H01L23/522 ,  H01L23/5227 ,  H01L2224/48091 ,  H01L2224/48227 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/106 ,  H01L2924/00014

摘要： LSI chip construction having a semiconductor body with a plurality of transistors formed in the semiconductor body in a predetermined pattern and a plurality of resistors formed in a semiconductor body in a predetermined pattern. Means is provided which includes two layers of metallization having input and output pads adjacent the outer perimeter of the body and contacting said transistors and resistors to form a plurality of emitter-follower circuits with certain of the emitter-follower circuits being made up of larger transistors and being located near the perimeter of the chip and near the input-output pads. The other emitter coupled circuits are clustered in groups to form an array of such groups with each of the groups being capable of containing a plurality of logic circuits.

摘要翻译： LSI芯片结构具有以预定图案形成在半导体本体中的多个晶体管的半导体本体和以预定图案形成在半导体本体中的多个电阻器。 提供了包括两层金属化的装置，其具有与主体的外周边相邻的输入和输出焊盘，并接触所述晶体管和电阻器以形成多个射极跟随器电路，其中某些射极跟随器电路由较大的晶体管 并且位于芯片的周边附近并且靠近输入 - 输出焊盘。 其他发射极耦合电路被分组成群，以形成这样的组的阵列，其中每个组能够包含多个逻辑电路。