公开(公告)号：US20220359551A1

公开(公告)日：2022-11-10

申请号：US17872534

申请日：2022-07-25

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L27/11536 ,  H01L27/06 ,  H01L27/11539 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788

摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US20220358971A1

公开(公告)日：2022-11-10

申请号：US17669189

申请日：2022-02-10

申请人： Micron Technology, Inc.

发明人： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC分类号： G11C5/10 ,  H01L27/108 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06

摘要： Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11495691B2

公开(公告)日：2022-11-08

申请号：US17056072

申请日：2019-05-27

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Toshihiko Takeuchi ,  Naoto Yamade ,  Yutaka Okazaki ,  Sachiaki Tezuka ,  Shunpei Yamazaki

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L29/792

摘要： The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

公开(公告)号：US11495596B2

公开(公告)日：2022-11-08

申请号：US16147512

申请日：2018-09-28

申请人： Intel Corporation

发明人： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC分类号： H01L27/06 ,  H01L27/07 ,  H01L25/18 ,  H01L29/51 ,  H01L27/02 ,  H01L29/88 ,  H01L27/11519

摘要： An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

公开(公告)号：US20220352154A1

公开(公告)日：2022-11-03

申请号：US17488830

申请日：2021-09-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Yang Chia

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

摘要： An integrated circuit (IC) manufacturing method includes: forming, in a device region of the semiconductor wafer, fins of fin field-effect transistors (finFETs) of the IC; forming, in a seal ring region surrounding the device region, at least one seal ring comprising fins encircling the device region and a monitoring pattern comprising fins encircling the device region; and forming, in the device region, gates of the finFETs of the IC. Polysilicon structures are formed on the fins of the monitoring pattern in a connecting region of the monitoring pattern. An epitaxial material is grown on the fins of the monitoring pattern between the polysilicon structures by a combination of epitaxial growth upward from the fins and epitaxial growth inward from the polysilicon structures. At least one electrical contact is formed that electrically contacts the epitaxial material.

公开(公告)号：US11489457B2

公开(公告)日：2022-11-01

申请号：US16780267

申请日：2020-02-03

申请人： DENSO CORPORATION

发明人： Shingo Tsuchimochi ,  Seita Iwahashi

IPC分类号： H01L23/373 ,  H02M7/537 ,  H01L27/06 ,  H02M7/00 ,  H01L25/07 ,  H01L23/433 ,  H01L23/495 ,  H02M7/493 ,  H01L23/00

摘要： A semiconductor module may include a plurality of semiconductor elements; and a first power terminal, a second power terminal and a third power terminal electrically connected to the plurality of semiconductor elements. The plurality of semiconductor elements may include at least one upper arm switching element electrically connected between the first power terminal and the second power terminal; and at least one lower arm switching element electrically connected between the second power terminal and the third power terminal. A number of the at least one upper arm switching element may be different from a number of the at least one lower arm switching element.

公开(公告)号：US11488950B2

公开(公告)日：2022-11-01

申请号：US17173611

申请日：2021-02-11

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Uzma B. Rana ,  Vibhor Jain ,  Anthony K. Stamper ,  Qizhi Liu ,  Siva P. Adusumilli

IPC分类号： H01L27/06 ,  H01L29/732 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73

摘要： Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

公开(公告)号：US11482438B2

公开(公告)日：2022-10-25

申请号：US17340004

申请日：2021-06-05

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/82 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

公开(公告)号：US20220336456A1

公开(公告)日：2022-10-20

申请号：US17361381

申请日：2021-06-29

申请人： Samsung Electronics Co., Ltd.

发明人： BYOUNGHAK HONG ,  Seunghyun Song

IPC分类号： H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06

摘要： Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

公开(公告)号：US20220336445A1

公开(公告)日：2022-10-20

申请号：US17804614

申请日：2022-05-31

申请人： Peter Hugh Blair

发明人： Peter Hugh Blair

IPC分类号： H01L27/06 ,  H01L21/8249

摘要： This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.