公开(公告)号：US20240178055A1

公开(公告)日：2024-05-30

申请号：US18509190

申请日：2023-11-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thierno Moussa BAH ,  Pascal GOURAUD ,  Patrick GROS D'AILLON ,  Emilie PREVOST

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768 ,  H01L29/94

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/30617 ,  H01L21/30625 ,  H01L21/76831 ,  H01L29/945

Abstract: The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.

公开(公告)号：US20240170586A1

公开(公告)日：2024-05-23

申请号：US18426090

申请日：2024-01-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud TOURNIER ,  Boris RODRIGUES GONCALVES ,  Frederic LALANNE ,  Pascal FONTENEAU

IPC: H01L31/02 ,  H01L27/146

CPC classification number: H01L31/02019 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L31/02005 ,  H01L27/14643

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

公开(公告)号：US20240170451A1

公开(公告)日：2024-05-23

申请号：US18504895

申请日：2023-11-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Come De Buttet ,  Damien Jeanjean ,  Sebastien Mermoz ,  Marc Neyens

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/83047 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: According to one aspect, there is proposed a method for assembling two integrated circuit wafers. The method includes removing by abrasion of a portion of an assembly face of a first wafer on a perimeter of the first wafer, and bonding the assembly face of the first wafer to an assembly face of a second integrated circuit wafer.

公开(公告)号：US20240162328A1

公开(公告)日：2024-05-16

申请号：US18387627

申请日：2023-11-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Edoardo BREZZA ,  Nicolas GUITARD ,  Gregory AVENIER

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66234 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004

Abstract: A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.

公开(公告)号：US11978756B2

公开(公告)日：2024-05-07

申请号：US17128608

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Sonarith Chhun

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1464

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US11961868B2

公开(公告)日：2024-04-16

申请号：US18198384

申请日：2023-05-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/14616

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

公开(公告)号：US11948950B2

公开(公告)日：2024-04-02

申请号：US17224720

申请日：2021-04-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Fourel ,  Laurent-Luc Chapelon

IPC: H01L27/146 ,  G02B1/10 ,  G02B1/14 ,  G02B3/00

CPC classification number: H01L27/14621 ,  G02B1/10 ,  G02B1/14 ,  G02B3/0012 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

公开(公告)号：US11947202B2

公开(公告)日：2024-04-02

申请号：US18295121

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sébastien Cremer ,  Frédéric Boeuf ,  Stephane Monfray

IPC: G02F1/01 ,  G02B6/12 ,  G02F1/035

CPC classification number: G02F1/035 ,  G02B6/12004 ,  G02F1/0147 ,  G02F2201/063

Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

公开(公告)号：US20240097030A1

公开(公告)日：2024-03-21

申请号：US18190893

申请日：2023-03-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien CREMER ,  Tadeu MOTA FRUTUOSO ,  Xavier GARROS ,  Blandine DURIEZ

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/84 ,  H01L27/1203

Abstract: The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.

公开(公告)号：US20240096898A1

公开(公告)日：2024-03-21

申请号：US18190897

申请日：2023-03-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Tadeu MOTA FRUTUOSO ,  Xavier GARROS ,  Blandine DURIEZ ,  Sebastien CREMER

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/84

Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.