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公开(公告)号：US11843008B2
公开(公告)日：2023-12-12
申请号：US17498286
申请日：2021-10-11
Inventor： Francois Guyader , Sara Pellegrini , Bruce Rae
IPC: H01L27/146 , G01J1/44 , H01L31/107 , H04N25/70
CPC classification number: H01L27/1461 , G01J1/44 , H01L27/14634 , H01L31/107 , H04N25/70 , G01J2001/4466
Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
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公开(公告)号：US11818883B2
公开(公告)日：2023-11-14
申请号：US17540029
申请日：2021-12-01
Inventor： Abderrezak Marzaki , Mathieu Lisart , Benoit Froment
CPC classification number: H10B20/367 , G11C16/0466 , H01L23/57
Abstract: The present description concerns a ROM including at least one first rewritable memory cell.
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公开(公告)号：US11817353B2
公开(公告)日：2023-11-14
申请号：US17568500
申请日：2022-01-04
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Pascal Chevalier , Alexis Gauthier , Gregory Avenier
IPC: H01L21/8222 , H01L21/265 , H01L27/06 , H01L29/06 , H01L29/66 , H01L29/737 , H01L29/93
CPC classification number: H01L21/8222 , H01L21/26513 , H01L27/0664 , H01L29/0649 , H01L29/66174 , H01L29/66242 , H01L29/7371 , H01L29/93
Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
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公开(公告)号：US11800821B2
公开(公告)日：2023-10-24
申请号：US17856711
申请日：2022-07-01
Inventor： Philippe Boivin , Daniel Benoit , Remy Berthelon
CPC classification number: H10N70/231 , H10B63/30 , H10N70/021 , H10N70/826
Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
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公开(公告)号：US11798937B2
公开(公告)日：2023-10-24
申请号：US17503621
申请日：2021-10-18
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Edoardo Brezza , Alexis Gauthier
IPC: H01L29/66 , H01L21/22 , H01L27/082 , H01L21/225 , H01L21/265 , H01L21/8222 , H01L29/737 , H01L29/732 , H01L29/08
CPC classification number: H01L27/0825 , H01L21/2205 , H01L21/2253 , H01L21/26513 , H01L21/8222 , H01L29/0821 , H01L29/66242 , H01L29/732 , H01L29/737 , H01L29/7371
Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.
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Patent Agency Ranking
716.发明公开公开(公告)号：US20230326947A1
公开(公告)日：2023-10-12
申请号：US18131543
申请日：2023-04-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Magali GREGOIRE , Joel SCHMITT
IPC: H01L27/146
CPC classification number: H01L27/14634 , H01L27/1469 , H01L27/14636
Abstract: An integrated circuit includes at least one silicon region and at least one metal pillar in contact with the at least one silicon region at an ohmic coupling region. The at least one metal pillar is formed by: depositing a layer of titanium on the at least one silicon region; depositing atomic layers of titanium nitride on the layer of titanium; and annealing at a temperature of between 715° C. and 815° C. for a period of between 5 seconds and 30 seconds. This forms a titanium silicide for the ohmic coupling region in a volume having the appearance of a spherical cap or segment.
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公开(公告)号：US11757054B2
公开(公告)日：2023-09-12
申请号：US17324619
申请日：2021-05-19
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Didier Dutartre
IPC: H01L31/028 , G01S7/4865 , H01L27/146 , H01L31/103
CPC classification number: H01L31/028 , G01S7/4865 , H01L27/14649 , H01L31/1037
Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.
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公开(公告)号：US11754758B2
公开(公告)日：2023-09-12
申请号：US17482237
申请日：2021-09-22
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Vincent Farys , Alain Inard , Olivier Noblanc
CPC classification number: G02B5/0263 , C23C16/345 , C23C16/56 , C23C18/1208 , G02B5/0236 , G02B5/0268
Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.
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公开(公告)号：US20230280630A1
公开(公告)日：2023-09-07
申请号：US18317705
申请日：2023-05-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.
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公开(公告)号：US20230194787A1
公开(公告)日：2023-06-22
申请号：US18167392
申请日：2023-02-10
Inventor： Frédéric BOEUF , Luca Maggi
CPC classification number: G02B6/124 , G02B6/34 , G02B6/43 , G02B6/30 , G02B6/12004 , G02B6/136 , G02B2006/12061
Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
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