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    Integrated device comprising a matrix of OLED active pixels with improved dynamic range
    711.
    发明授权
    Integrated device comprising a matrix of OLED active pixels with improved dynamic range 有权
    包括具有改进的动态范围的OLED有源像素矩阵的集成器件

    公开(公告)号：US09521723B2

    公开(公告)日：2016-12-13

    申请号：US14723942

    申请日：2015-05-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Jerome Nebon ,  Christophe Forel

    IPC: H01L27/32 ,  H05B33/08 ,  G09G3/32

    CPC classification number: H05B33/0896 ,  G09G3/3233 ,  G09G2300/0814 ,  G09G2320/0247 ,  G09G2320/045

    Abstract: An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

    Abstract translation: 集成器件包括其中形成有有源像素的矩阵的半导体衬底。 每个有源像素包括OLED二极管，其源极耦合到OLED二极管的阳极的第一nMOS晶体管，以及耦合到第一nMOS晶体管的栅极的刷新电路。 第一个nMOS晶体管具有其源极及其衬底耦合在一起。 第一nMOS晶体管位于半导体衬底的第一部分中并且位于半导体衬底的第一部分上，并且刷新电路位于半导体衬底的第二部分中并位于半导体衬底的第二部分上，其中第一部分和第二部分彼此电绝缘。

    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
    713.
    发明授权
    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking 有权
    使用片上时钟设计的ATPG故障的即时测试和调试逻辑

    公开(公告)号：US09482719B2

    公开(公告)日：2016-11-01

    申请号：US14152130

    申请日：2014-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G06F11/00 ,  G01R31/317 ,  G01R31/3181

    CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

    Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

    Abstract translation: 半导体芯片包括接收ATPG测试图案并产生响应的时钟脉冲的OCC。 OCC测试电路检测OCC电路的时钟脉冲，并提供调试数据以测试输出可配置逻辑，其也接收来自测试不同DUT触发器的其他电路的结果。 削波测试电路通过向DUT I / O提供脉冲宽度敏感的触发器输出来检测来自OCC的剪辑时钟脉冲的ATPG故障。 IR跌落测试电路检测ATPG故障是否由于某些触发器中的IR降低问题。 脉冲位操作电路改变提供给OCC和OCC产生的时钟脉冲的测试模式。 连接到测试输出可配置逻辑的调试控制器在不同测试结果之间选择供应作为输出测试信号，与ATE上的预期模式数据进行比较，并用于隔离芯片上的错误。

    Driver circuit including driver transistors with controlled body biasing
    714.
    发明授权
    Driver circuit including driver transistors with controlled body biasing 有权
    驱动电路包括具有受控体偏置的驱动晶体管

    公开(公告)号：US09473135B2

    公开(公告)日：2016-10-18

    申请号：US14500076

    申请日：2014-09-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

    IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

    CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

    Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

    Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

    Conditional pulse generator circuit for low power pulse triggered flip flop
    716.
    发明授权
    Conditional pulse generator circuit for low power pulse triggered flip flop 有权
    条件脉冲发生器电路用于低功率脉冲触发触发器

    公开(公告)号：US09401715B1

    公开(公告)日：2016-07-26

    申请号：US14718204

    申请日：2015-05-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Alok Kumar Tripathi ,  Priyankar Mathuria

    IPC: H03K3/356 ,  H03K19/00

    CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356173

    Abstract: An electronic device includes a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal. A pulse generation circuit is configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.

    Abstract translation: 电子设备包括脉冲锁存电路，其被配置为基于接收到脉冲信号将数据输入信号锁存到输出端。 脉冲发生电路被配置为将数据输入信号和脉冲锁存电路的输出端的输出信号进行比较，并且响应于时钟信号，基于它们之间的失配产生脉冲信号。

    Suspend mode in charge pump
    718.
    发明授权
    Suspend mode in charge pump 有权
    电荷泵暂停模式

    公开(公告)号：US09385593B2

    公开(公告)日：2016-07-05

    申请号：US14482714

    申请日：2014-09-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Shyam Somayajula ,  Sri Ram Gupta ,  Lionel Cimaz

    IPC: H04R3/00 ,  H03F3/217 ,  H02M3/07 ,  H03F3/187 ,  H03F3/45 ,  H02M1/00

    CPC classification number: H02M3/07 ,  H02M2001/0032 ,  H02M2001/0035 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  Y02B70/16

    Abstract: A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load.

    Abstract translation: 设备可以与电源相关联。 该装置可以包括电荷泵，其被配置为基于来自电源的输入电压输出脉宽调制电压，其中脉宽调制电压在第一电压和第二电压之间变化。 器件还可以包括包括输出电容器的低通滤波器，输出电容器被配置为平均脉冲宽度调制电压并输出具有与输入电压值不同的值的滤波电压。 该装置还可以包括控制器，其被配置为当施加在低通滤波器上的负载低于阈值负载时，选择性地将电荷泵与电源分离。

    ELECTRONIC DEVICE INCLUDING PICO PROJECTOR AND OPTICAL CORRECTION SYSTEM
    719.
    发明申请
    ELECTRONIC DEVICE INCLUDING PICO PROJECTOR AND OPTICAL CORRECTION SYSTEM 有权
    电子设备，包括PICO投影机和光学校正系统

    公开(公告)号：US20160187765A1

    公开(公告)日：2016-06-30

    申请号：US14584080

    申请日：2014-12-29

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Tzvi Philipp

    IPC: G03B21/14 ,  G02B27/00 ,  G03B21/28 ,  G02B26/08 ,  G02B17/08

    CPC classification number: G03B21/147 ,  G02B17/0852 ,  G02B17/0896 ,  G02B26/0816 ,  G02B27/0068 ,  G03B21/142 ,  G03B21/28 ,  H04N9/317 ,  H04N9/3173

    Abstract: An electronic device includes a movable mirror system to selectively reflect an incident image projection beam traveling along a first path toward a second path different than a first path. The image projection beam displays a corrected image at a first location but would otherwise display an uncorrected image at a second location when the movable mirror system reflects the image projection beam toward the second path. The electronic device also includes an optical correction system having at least one corrective optic element to correct the image projection beam to display a corrected image at the second location when the movable mirror system reflects the image projection beam toward the second path.

    Abstract translation: 电子设备包括可移动镜系统，用于选择性地将沿着第一路径行进的入射图像投影光束朝向与第一路径不同的第二路径反射。 图像投影光束在第一位置显示校正图像，但是当可移动反射镜系统将图像投影光束朝向第二路径反射时，否则将在第二位置处显示未校正的图像。 电子设备还包括光学校正系统，其具有至少一个校正光学元件，以在可移动镜像系统将图像投射束朝向第二路径反射时校正图像投影光束以在第二位置显示校正图像。

    DATA RECEIVING DEVICE INCLUDING AN ENVELOPE DETECTOR AND RELATED METHODS
    720.
    发明申请
    DATA RECEIVING DEVICE INCLUDING AN ENVELOPE DETECTOR AND RELATED METHODS 有权
    数据接收装置，包括信封检测器及相关方法

    公开(公告)号：US20160187392A1

    公开(公告)日：2016-06-30

    申请号：US14585357

    申请日：2014-12-30

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Daljeet KUMAR ,  Tapas NANDY ,  Surendra KUMAR

    IPC: G01R19/04

    CPC classification number: G01R19/04 ,  G01R19/2503

    Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

    Abstract translation: 数据接收设备可以包括包络检测器，其可以包括被配置为接收差分输入信号的第一和第二输入，耦合到第一输入并被配置为产生第一和第二检测器输出的第一对检测器，以及第二对检测器 耦合到第二输入并且被配置为产生第三和第四检测器输出。 包络检测器还可以包括被配置为基于第一和第三检测器产生复位的逻辑电路。 数据接收装置还可以包括耦合到包络检测器的接收器电路，并被配置成随着复位产生基于第二和第四检测器的输出，以及耦合到接收器电路的第一位检测电路。

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