公开(公告)号：US20150001645A1

公开(公告)日：2015-01-01

申请号：US14316583

申请日：2014-06-26

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics International N.V.

Inventor： Dino Faralli ,  Benedetto Vigna ,  Laura Maria Castoldi

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/012 ,  B81C1/00269 ,  B81C2203/0118 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/10155 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A MEMS device wherein a die of semiconductor material has a first face and a second face. A membrane is formed in or on the die and faces the first surface. A cap is fixed to the first face of the first die and is spaced apart from the membrane by a space. The die is fixed, on its second face, to an ASIC, which integrates a circuit for processing the signals generated by the die. The ASIC is in turn fixed on a support. A packaging region coats the die, the cap, and the ASIC and seals them from the outside environment. A fluidic path is formed through the support, the ASIC, and the first die, and connects the membrane and the first face of the die with the outside, without requiring holes in the cap.

Abstract translation: 一种MEMS器件，其中半导体材料的管芯具有第一面和第二面。 在模具中或模具上形成膜并面向第一表面。 盖子固定在第一模具的第一面上并且与隔膜隔开一个空间。 芯片在其第二面被固定到ASIC，其集成了用于处理由芯片产生的信号的电路。 ASIC依次固定在支持上。 包装区域涂覆模具，盖子和ASIC，并将它们与外部环境密封。 通过支撑件，ASIC和第一模具形成流体路径，并且将膜和模具的第一面与外部连接，而不需要在盖中的孔。

公开(公告)号：US08922256B1

公开(公告)日：2014-12-30

申请号：US13971373

申请日：2013-08-20

Applicant: STMicroelectronics International N.V.

Inventor： Surendra Kumar

IPC: H03K3/00

CPC classification number: H03K17/687 ,  H03K17/0422

Abstract: An apparatus includes a number of current steering switches and a power controller. A current source is coupled to the current steering switches and to the power controller. The current source is controlled to provide a first voltage to the current steering switches. The apparatus also includes a number of pre-drivers. The power controller is configured to provide a second voltage to the plurality of pre-drivers. The second voltage is dependent on the first voltage.

Abstract translation: 一种装置包括多个当前的转向开关和功率控制器。 电流源耦合到当前的转向开关和功率控制器。 控制电流源以向当前的转向开关提供第一电压。 该装置还包括若干预驱动器。 功率控制器被配置为向多个预驱动器提供第二电压。 第二电压取决于第一电压。

公开(公告)号：US20140372823A1

公开(公告)日：2014-12-18

申请号：US13919884

申请日：2013-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Ajay Kumar Dimri

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/318552

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

Abstract translation: 一种装置具有大的同步逻辑块，其被布置成包括第一分区和第二分区。 第一分区被配置为在功能模式期间和测试模式期间接收第一时钟信号。 第二分区被配置为在功能模式期间接收第一时钟信号，并且第二分区被配置为在测试模式期间接收第二时钟信号。 第二时钟信号具有与第一时钟信号相同的频率。 第二时钟信号与第一时钟信号具有不同的相位。

公开(公告)号：US08913457B2

公开(公告)日：2014-12-16

申请号：US14271165

申请日：2014-05-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, SA

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。

公开(公告)号：US20140365987A1

公开(公告)日：2014-12-11

申请号：US13911224

申请日：2013-06-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Manoj Kumar ,  Jean Guillorit ,  Navin Kumar Dayani

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.

Abstract translation: 输入/输出电路布局具有第一部分，其中具有较厚栅极氧化物的第一晶体管位于其中，第二部分中具有较薄栅极氧化物的第二晶体管位于其中。 由于工艺技术的限制，所有第二晶体管的栅极定向在单一的共同方向。 第二部分具有包括与第一边缘相邻的第一边缘和第二边缘的正方形形状的周边。 耦合到第二晶体管的第一连接引脚具有从第一边缘向内并垂直于第一边缘延伸的取向。 耦合到第二晶体管的第二连接引脚具有从所述第二边缘向内并垂直于所述第二边缘延伸的取向。 在相邻的第一和第二边缘上的方形形状和销的存在允许第二部分的旋转以适应布局的不同取向。

公开(公告)号：US08907973B2

公开(公告)日：2014-12-09

申请号：US13656869

申请日：2012-10-22

Applicant: STMicroelectronics International N.V.

Inventor： Chandranath Manchi

IPC: G09G5/00 ,  G09G5/02 ,  G06T15/60 ,  G06T17/00 ,  H04N7/12 ,  H04N5/00 ,  H04N5/52 ,  H04B1/10 ,  G06K9/40 ,  G06K9/36 ,  G06K9/32 ,  G06F15/00 ,  G06F17/10 ,  G06F11/00

CPC classification number: G06T5/003 ,  G06T3/4007 ,  G06T5/20 ,  G06T2207/10024

Abstract: An image processor includes generates a content adaptive kernel from an image block with noise of a luminance component signal with a low resolution. The content adaptive kernel is convolved with the luminance component signal. A noise signal and an extracted texture which excludes noise are generated. The luminance component signal is filtered as function of the noise signal to generate an enhanced luminance component signal. Horizontal and vertical scaling is performed on the enhanced luminance component signal, the extracted texture, and the luminance component signal, with the luminance component signal adaptively scaled as a function of the extracted texture. The horizontally and vertically scaled enhanced luminance component signal, extracted texture and luminance component signal are then combined to generate an output luminance component signal with a high resolution.

Abstract translation: 图像处理器包括从具有低分辨率的亮度分量信号的噪声的图像块生成内容自适应内核。 内容自适应内核与亮度分量信号进行卷积。 产生排除噪声的噪声信号和提取纹理。 亮度分量信号作为噪声信号的函数被滤波，以产生增强的亮度分量信号。 对增强的亮度分量信号，提取的纹理和亮度分量信号进行水平和垂直缩放，其中亮度分量信号作为提取的纹理的函数自适应地缩放。 然后组合水平和垂直缩放的增强亮度分量信号，提取的纹理和亮度分量信号以产生具有高分辨率的输出亮度分量信号。

公开(公告)号：US20140334643A1

公开(公告)日：2014-11-13

申请号：US14311086

申请日：2014-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Carlo Pinna ,  Alessandro Mecchia ,  Paolo Pesenti

IPC: H03G3/20

CPC classification number: H03G3/20 ,  H03G3/301 ,  H04R1/005 ,  H04R1/04 ,  H04R3/04 ,  H04R2499/11

Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal. Furthermore, the digital microphone comprises an Automatic Gain Controller block 25, arranged to detect the digital signal and to generate said gain control signal, on the basis of the detected digital signal. The Automatic Gain Controller block is further arranged to generate the compensation signal, on the basis of the control signal, and to provide the compensation signal to the compensation block, to compensate a variation of the digital signal resulting from the variable gain of the preamplifier. Finally, the digital microphone device comprises a conversion block, arranged to receive the compensated signal and to convert it into the single-bit PDM output signal.

Abstract translation: 本公开涉及提供单位脉冲密度调制PDM输出信号的数字麦克风装置。 数字麦克风包括麦克风，其布置成将声输入信号转换为模拟电信号，以及具有可变增益的前置放大器，其布置成接收模拟电信号并根据可变增益提供放大的模拟电信号 。 可变增益取决于增益控制信号。 数字麦克风还包括模数转换器模块，被布置为接收放大的模拟电信号并将其转换成相应的数字信号; 以及补偿块，被布置成基于补偿信号接收数字信号并对这种数字信号执行数字操作，以产生补偿信号。 此外，数字麦克风包括自动增益控制器块25，其被布置为基于检测到的数字信号来检测数字信号并产生所述增益控制信号。 自动增益控制器块还被布置成基于控制信号产生补偿信号，并且向补偿块提供补偿信号，以补偿由前置放大器的可变增益引起的数字信号的变化。 最后，数字麦克风装置包括转换块，被布置成接收经补偿的信号并将其转换成单位PDM输出信号。

公开(公告)号：US08879222B2

公开(公告)日：2014-11-04

申请号：US13626131

申请日：2012-09-25

Applicant: STMicroelectronics International N.V.

Inventor： Gaurav Singh

IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.

Abstract translation: 电路包括被配置为放电静电电荷的放电装置。 放电装置具有放电状态。 第一电路被配置为当感测静电电荷时向放电装置提供脉冲。 脉冲使排出装置进入排出状态。 第二电路被配置为在脉冲结束之后将放电配置保持在放电状态。 第三电路被配置为接收脉冲并向放电装置提供延迟的输出。 延迟输出导致放电装置退出放电状态。

公开(公告)号：US08878710B2

公开(公告)日：2014-11-04

申请号：US13677674

申请日：2012-11-15

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Neha Bhargava ,  Anupam Jain

IPC: H03M3/00 ,  H03M1/12

CPC classification number: H03M3/30 ,  H03M3/344 ,  H03M3/376 ,  H03M3/462

Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

Abstract translation: 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。

公开(公告)号：US20140293723A1

公开(公告)日：2014-10-02

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。