中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4934 records (took 0.04 seconds)

    Load multiple primitives per thread in a graphics pipeline
    72.
    发明授权
    Load multiple primitives per thread in a graphics pipeline 有权

    公开(公告)号：US12062126B2

    公开(公告)日：2024-08-13

    申请号：US17489008

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

    IPC: G06T15/00

    CPC classification number: G06T15/005

    Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.

    Memory control for data processing pipeline optimization
    73.
    发明授权
    Memory control for data processing pipeline optimization 有权

    公开(公告)号：US12056352B2

    公开(公告)日：2024-08-06

    申请号：US17955286

    申请日：2022-09-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Harris Eleftherios Gasparakis

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

    Abstract: Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization instructions to control how memory operations are performed for a specific data processing pipeline during execution. In implementations, the optimization instructions cause a memory system to discard data (e.g., invalidate cache entries) without copying the discarded data to another storage location after the data is no longer needed by the pipeline. The optimization instructions alternatively or additionally control at least one of evicting, writing-back, or prefetching data to minimize latency during pipeline execution.

    GENERATING KEYS FOR A CLUSTER OF NODES IN A SINGLE SECURITY ASSOCIATION
    74.
    发明公开
    GENERATING KEYS FOR A CLUSTER OF NODES IN A SINGLE SECURITY ASSOCIATION 审中-公开

    公开(公告)号：US20240259194A1

    公开(公告)日：2024-08-01

    申请号：US18212739

    申请日：2023-06-22

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Donald Matthews, JR.

    IPC: H04L9/08 ,  H04L9/40

    CPC classification number: H04L9/0861 ,  H04L63/0428 ,  H04L9/3242

    Abstract: A computing node in a computing cluster includes at least a key generator and an encryption engine. The key generator implements a key derivation function and generates a first data encryption key based on a key derivation key. The key derivation key is a global security association encryption key shared by a plurality of nodes in the computing cluster. The first data encryption key is unique to a node pair comprising the first node and a second node of the plurality of nodes. The encryption engine encrypts a data packet using the first data encryption key.

    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN
    75.
    发明公开
    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN 审中-公开

    公开(公告)号：US20240258322A1

    公开(公告)日：2024-08-01

    申请号：US18401038

    申请日：2023-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673

    Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

    Split read port latch array bit cell
    79.
    发明授权
    Split read port latch array bit cell 有权

    公开(公告)号：US12033721B2

    公开(公告)日：2024-07-09

    申请号：US17359446

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

    Register compaction with early release
    80.
    发明授权
    Register compaction with early release 有权

    公开(公告)号：US12033238B2

    公开(公告)日：2024-07-09

    申请号：US17030852

    申请日：2020-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brian D. Emberling ,  Joseph Lee Greathouse ,  Anthony Thomas Gutierrez

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/60 ,  G06T1/20

    Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.

Patent Agency Ranking