公开(公告)号：US07479236B2

公开(公告)日：2009-01-20

申请号：US11612355

申请日：2006-12-18

Applicant: Jack Chen ,  Andrew D Bailey, III ,  Ben Mooring ,  Stephen J. Cain

Inventor： Jack Chen ,  Andrew D Bailey, III ,  Ben Mooring ,  Stephen J. Cain

IPC: G01L21/30 ,  G05B15/00

CPC classification number: G05B19/41875 ,  G05B2219/37398 ,  G05B2219/45031 ,  G05B2219/50057 ,  Y02P90/22

Abstract: A method for calculating a process center for a chuck in a processing chamber is provided. The method includes generating pre-processing and post-processing measurement data points, which is perform by measuring thickness of a film substrate at a set of orientations and a set of distances from a geometric center of the substrate. The method also includes comparing the pre-processing and post-processing measurement data points to calculate a set of etch depth numbers. The method further includes generating etch profiles for the set of orientations. The method yet also includes extrapolating a set of radiuses, which is associated with a first etch depth, from the etch profiles. The method yet further includes generating an off-centered plot, which is a graphical representation of the set of radiuses versus the set of orientations. The method more over includes calculating the process center by applying a curve-fitting equation to the off-centered plot.

Abstract translation: 提供了一种用于计算处理室中的卡盘的处理中心的方法。 该方法包括产生预处理和后处理测量数据点，其通过以一组取向和距衬底几何中心的一组距离测量薄膜衬底的厚度来执行。 该方法还包括比较预处理和后处理测量数据点以计算一组蚀刻深度数。 该方法还包括为该组取向生成蚀刻轮廓。 该方法还包括从蚀刻轮廓推断与第一蚀刻深度相关联的一组半径。 该方法还包括生成偏心图，其是该组半径与该组取向的图形表示。 更多的方法包括通过对偏心图应用曲线拟合方程来计算过程中心。

公开(公告)号：US07164282B1

公开(公告)日：2007-01-16

申请号：US11092849

申请日：2005-03-28

Applicant: Andrew D. Bailey, III ,  Michael Leonard ,  Benjamin W. Mooring ,  Candi Kristoffersen

Inventor： Andrew D. Bailey, III ,  Michael Leonard ,  Benjamin W. Mooring ,  Candi Kristoffersen

IPC: G01R31/26

CPC classification number: G01N27/9046

Abstract: A method of determining an average electrical response to a conductive layer on a set of substrates vibrating about a vibration mean is disclosed. The method includes positioning a sensor near a position on a first substrate; and measuring a first plurality of electrical responses, wherein each of the first plurality of electrical responses is function of an electrical film property response and a first substrate proximity response. The method also includes positioning the sensor near the position on a second substrate; and measuring a second plurality of electrical responses, wherein each of the second plurality of electrical responses is function of the electrical film property response and a second substrate proximity response. The method further includes determining a first average electrical response for the first substrate and a second average electrical response for the second substrate, wherein a difference between an average first substrate proximity response and an average second substrate proximity response is about zero.

Abstract translation: 公开了一种确定围绕振动平均值振动的一组基底上的导电层的平均电响应的方法。 该方法包括将传感器定位在第一基底上的位置附近; 以及测量第一多个电响应，其中所述第一多个电响应中的每一个是电膜性质响应和第一衬底接近响应的函数。 该方法还包括将传感器定位在第二基底上的位置附近; 以及测量第二多个电响应，其中所述第二多个电响应中的每一个是所述电膜特性响应和第二基板接近响应的函数。 该方法还包括确定第一衬底的第一平均电响应和第二衬底的第二平均电响应，其中平均第一衬底接近响应和平均第二衬底接近响应之间的差为约零。

公开(公告)号：US07130767B2

公开(公告)日：2006-10-31

申请号：US10951551

申请日：2004-09-27

Applicant: Andrew D. Bailey, III ,  Puneet Yadav

Inventor： Andrew D. Bailey, III ,  Puneet Yadav

IPC: G06F11/32

CPC classification number: H01J37/32935

Abstract: A computer-implemented data presentation technique for presenting a set of expected failure states of system-related constructs pertaining to a plasma processing system is disclosed. The technique includes receiving a set of indicia pertaining to a first system-related construct of said system-related constructs. The technique also includes computing, in accordance with a first sub-method and responsive to said receiving said first set of indicia, a first expected failure state value. The technique further includes computing a first normalized expected failure state value in accordance with a first weight; correlating said first normalized expected failure state value to a first color; and displaying said first color in a cell of an n-dimensional matrix, wherein n is a number greater than 1.

Abstract translation: 公开了一种用于呈现与等离子体处理系统有关的系统相关结构的一组预期故障状态的计算机实现的数据呈现技术。 该技术包括接收与所述系统相关结构的第一系统相关结构有关的一组标记。 该技术还包括根据第一子方法并响应于所述接收所述第一组标记来计算第一预期故障状态值。 该技术还包括根据第一权重来计算第一归一化预期故障状态值; 将所述第一归一化预期故障状态值与第一颜色相关; 以及在n维矩阵的单元格中显示所述第一颜色，其中n是大于1的数字。

公开(公告)号：US07086347B2

公开(公告)日：2006-08-08

申请号：US10140618

申请日：2002-05-06

Applicant: Arthur M. Howald ,  Andras Kuthi ,  Andrew D. Bailey, III ,  Butch Berney

Inventor： Arthur M. Howald ,  Andras Kuthi ,  Andrew D. Bailey, III ,  Butch Berney

IPC: H01L21/00 ,  C23C16/00

CPC classification number: H01J37/32477 ,  H01J37/32623

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward a plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

公开(公告)号：US07078344B2

公开(公告)日：2006-07-18

申请号：US10769498

申请日：2004-01-30

Applicant: Andrew D. Bailey, III ,  Michael Ravkin ,  Mikhail Korolik ,  Puneet Yadav

Inventor： Andrew D. Bailey, III ,  Michael Ravkin ,  Mikhail Korolik ,  Puneet Yadav

IPC: H01L21/302

CPC classification number: H01L21/7684 ,  H01J37/32522 ,  H01J2237/022 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67253

Abstract: A system and method for planarizing and controlling non-uniformity on a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple features in the pattern. The conductive interconnect material having an overburden portion. A bulk of the overburden portion is removed and a remaining portion of the overburden portion has a non-uniformity. The non-uniformity is mapped, optimal solution determined and a dynamic liquid meniscus etch process recipe is developed to correct the non-uniformity. A dynamic liquid meniscus etch process, using the dynamic liquid meniscus etch process recipe, is applied to correct the non-uniformity to substantially planarize the remaining portion of the overburden portion.

Abstract translation: 用于平坦化和控制图案化半导体衬底上的不均匀性的系统和方法包括接收图案化的半导体衬底。 图案化的半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 去除大部分上覆层部分，并且覆盖层部分的剩余部分具有不均匀性。 绘制不均匀性，确定最佳溶液，并开发动态液体弯月面蚀刻工艺配方以校正不均匀性。 使用动态液体弯月面蚀刻工艺配方的动态液体弯月面蚀刻工艺来校正不均匀性，以使覆盖层部分的剩余部分基本平坦化。

公开(公告)号：US06922603B1

公开(公告)日：2005-07-26

申请号：US10327233

申请日：2002-12-20

Applicant: Andrew D. Bailey III

Inventor： Andrew D. Bailey III

IPC: G06F19/00 ,  H01L21/66

CPC classification number: H01L22/20

Abstract: A system and method of determining multiple uniformity metrics of a semiconductor wafer includes quantitatively defining a location metric of a nonuniformity on the surface of the wafer. A quantity is measured at multiple locations on a top surface of the wafer and a center of mass is of the nonuniformity is determined.

Abstract translation: 确定半导体晶片的多个均匀性度量的系统和方法包括定量地定义晶片表面上的不均匀性的位置度量。 在晶片的顶面上的多个位置处测量量，并且确定质心的不均匀性。

公开(公告)号：US09721782B2

公开(公告)日：2017-08-01

申请号：US13157122

申请日：2011-06-09

Applicant: Jack Chen ,  Andrew D. Bailey, III ,  Iqbal Shareef

Inventor： Jack Chen ,  Andrew D. Bailey, III ,  Iqbal Shareef

IPC: B05C11/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/67 ,  C23C16/455

CPC classification number: H01L21/02087 ,  C23C16/455 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67051 ,  H01L21/67069 ,  H01L21/6708

Abstract: A method for etching a bevel edge of a substrate in a processing chamber is provided. The method includes flowing an inert gas into a center region of the processing chamber defined above a center region of the substrate and flowing a mixture of an inert gas and a processing gas over an edge region of the substrate. The method further includes striking a plasma in the edge region, wherein the flow of the inert gas and the flow of the mixture maintain a mass fraction of the processing gas substantially constant. A processing chamber configured to clean a bevel edge of a substrate is also provided.

公开(公告)号：US08900398B2

公开(公告)日：2014-12-02

申请号：US12872982

申请日：2010-08-31

Applicant: Rajinder Dhindsa ,  Michael C. Kellogg ,  Babak Kadkhodayan ,  Andrew D. Bailey, III

Inventor： Rajinder Dhindsa ,  Michael C. Kellogg ,  Babak Kadkhodayan ,  Andrew D. Bailey, III

IPC: H01L21/3065 ,  H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32623

Abstract: An arrangement for performing pressure control within a processing chamber substrate processing is provided. The arrangement includes a peripheral ring configured at least for surrounding a confined chamber volume that is configured for sustaining a plasma for etching the substrate during substrate processing. The peripheral ring includes a plurality of slots that is configured at least for exhausting processed byproduct gas from the confined chamber volume during substrate processing. The arrangement also includes a conductive control ring that is positioned next to the peripheral ring and is configured to include plurality of slots. The pressure control is achieved by moving the conductive control ring relative to the peripheral ring such that a first slot on the peripheral ring and a second slot on the conductive control ring are offset with respect to one another in a range of zero offset to full offset.

Abstract translation: 提供了一种用于在处理室衬底处理中执行压力控制的装置。 该装置包括至少围绕限制室容积配置的外围环，该限定室容积被配置为在衬底处理期间维持用于刻蚀衬底的等离子体。 周边环包括多个狭槽，其被构造成至少在衬底处理期间从受限腔体积中排出经处理的副产物气体。 该布置还包括导电控制环，该导电控制环位于外围环旁边并且被配置为包括多个狭槽。 通过相对于外围环移动导电控制环来实现压力控制，使得外围环上的第一槽和导电控制环上的第二槽相对于彼此在零偏移到全偏移的范围内彼此偏移 。

公开(公告)号：US20140060739A1

公开(公告)日：2014-03-06

申请号：US13662331

申请日：2012-10-26

Applicant: Rajinder Dhindsa ,  Alexei Marakhtanov ,  Michael C. Kellogg ,  Andy Desepte ,  Andrew D. Bailey, III

Inventor： Rajinder Dhindsa ,  Alexei Marakhtanov ,  Michael C. Kellogg ,  Andy Desepte ,  Andrew D. Bailey, III

IPC: H01J37/04

CPC classification number: H01J37/04 ,  H01J37/32091 ,  H01J37/32174

Abstract: Methods and apparatus for operating the plasma processing chamber of a plasma processing tool in at least two modes are disclosed. In the first mode, the substrate-bearing assembly is movable within a gap-adjustable range to adjust the gap between the electrodes to accommodate different processing requirements. In this first mode, RF ground return path continuity is maintained irrespective of the gap distance as long as the gap distance is within the gap-adjustable range. In the second mode, the substrate bearing assembly is capable of moving to further open the gap to accommodate unimpeded substrate loading/unloading.

Abstract translation: 公开了以至少两种模式操作等离子体处理工具的等离子体处理室的方法和装置。 在第一模式中，基板支承组件可在间隙可调节范围内移动，以调节电极之间的间隙以适应不同的加工要求。 在该第一模式中，只要间隙距离在间隙可调整范围内，RF接地返回路径连续性被维持而与间隙距离无关。 在第二模式中，基板支承组件能够移动以进一步打开间隙以适应无阻碍的基板装载/卸载。

公开(公告)号：US08574397B2

公开(公告)日：2013-11-05

申请号：US13547700

申请日：2012-07-12

Applicant: Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

Inventor： Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

IPC: C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC classification number: H01L21/02087 ,  B08B7/0035 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32541 ,  H01L21/67069

Abstract: A plasma processing chamber configured for cleaning a bevel edge of a substrate is provided. The chamber includes a top edge electrode surrounding an insulating plate, and the insulator plate opposes a bottom electrode. The top edge electrode is electrically grounded and separated from the insulator plate by a top dielectric ring. The chamber also includes a bottom edge electrode that is electrically grounded and surrounds the bottom electrode and is separated from the bottom electrode by a bottom dielectric ring. The bottom edge electrode is oriented to oppose the top edge electrode, and the bottom edge electrode has an L shape that is up-facing. Bevel edge plasma processing of a substrate edge is configured to be processed in a chamber having the top and bottom edge electrodes.

Abstract translation: 提供了一种用于清洁基板的斜边缘的等离子体处理室。 该室包括围绕绝缘板的顶边电极，绝缘体板与底部电极相对。 顶边电极通过顶部介质环电接地并与绝缘体板分离。 该腔室还包括底部电极，其电接地并且围绕底部电极并且通过底部介电环与底部电极分离。 底边电极被定向为与顶边缘电极相对，并且底边电极具有面向上的L形。 衬底边缘的斜边等离子体处理被配置为在具有顶部和底部边缘电极的腔室中进行处理。