公开(公告)号：US20050179073A1

公开(公告)日：2005-08-18

申请号：US10722193

申请日：2003-11-26

Applicant: Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

Inventor： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10873 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/10888

Abstract: An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

Abstract translation: 集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。 源极区域和漏极区域在栅电极的交替侧上的有源区域中。 至少一个掩埋绝缘层位于漏极区域或源极区域之下。

公开(公告)号：US06890823B2

公开(公告)日：2005-05-10

申请号：US10426562

申请日：2003-04-30

Applicant: Byeong-chan Lee ,  Si-young Choi ,  Chul-sung Kim ,  Jong-ryeol Yoo ,  Deok-hyung Lee

Inventor： Byeong-chan Lee ,  Si-young Choi ,  Chul-sung Kim ,  Jong-ryeol Yoo ,  Deok-hyung Lee

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/6656

Abstract: Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

Abstract translation: 公开了在栅电极的侧壁上形成热氧化层的方法。 特别地，可以通过在集成电路基板上形成栅电极并使用热氧化工艺在栅电极的侧壁上形成热氧化层，在栅电极的侧壁上形成热氧化物层。 在形成热氧化物层之后，可以在栅电极上形成硅化物层。

公开(公告)号：US09190410B2

公开(公告)日：2015-11-17

申请号：US14466078

申请日：2014-08-22

Applicant: Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

Inventor： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

公开(公告)号：US20150008452A1

公开(公告)日：2015-01-08

申请号：US14492628

申请日：2014-09-22

Applicant: Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

Inventor： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

Abstract translation: 半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。 沟道区位于衬底上并位于第一和第二应力产生外延区之间。 栅电极在沟道区上。 沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

公开(公告)号：US20120112156A1

公开(公告)日：2012-05-10

申请号：US13220777

申请日：2011-08-30

Applicant: Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

Inventor： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

IPC: H01L45/00

CPC classification number: H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Abstract translation: 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。

公开(公告)号：US20120058609A1

公开(公告)日：2012-03-08

申请号：US13223783

申请日：2011-09-01

Applicant: Seung-Hun LEE ,  Byeong-Chan Lee ,  Sang-Bom Kang

Inventor： Seung-Hun LEE ,  Byeong-Chan Lee ,  Sang-Bom Kang

IPC: H01L21/8238 ,  H01L21/20

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

公开(公告)号：US20120034746A1

公开(公告)日：2012-02-09

申请号：US13241311

申请日：2011-09-23

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

Abstract translation: 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

公开(公告)号：US20110266627A1

公开(公告)日：2011-11-03

申请号：US13096311

申请日：2011-04-28

Applicant: Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

Inventor： Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

IPC: H01L27/092 ,  H01L27/085

CPC classification number: H01L21/823481 ,  H01L21/823878

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas.

Abstract translation: 半导体器件包括半导体衬底，其包括由器件隔离层限定的多个有源区，与多个有源区交叉的栅极线结构，半导体衬底上的缓冲绝缘层，缓冲绝缘层接触一侧的一部分 栅极线结构，缓冲绝缘层上的接触蚀刻停止层以及通过缓冲绝缘层和接触蚀刻阻挡层的接触插塞，以连接到多个有源区。

公开(公告)号：US20110076012A1

公开(公告)日：2011-03-31

申请号：US12889771

申请日：2010-09-24

Applicant: Yu Sik Na ,  Byeong Chan Lee

Inventor： Yu Sik Na ,  Byeong Chan Lee

IPC: H04B10/08

CPC classification number: H04B10/0799 ,  H04J3/1694 ,  H04Q11/0067 ,  H04Q2011/0064 ,  H04Q2011/0083

Abstract: Provided are an optical network terminal (ONT) and a method for the ONT to detect an optical transmission error. The ONT is connected with an optical line termination (OLT) and constituting a passive optical network (PON), and includes an optical transmitter configured to transmit an optical signal to the OLT, an error detector configured to detect an error of the optical transmitter; and a controller configured to transmit an error message to the OLT through the optical transmitter when the error detector detects an error of the optical transmitter.

Abstract translation: 提供了一种光网络终端（ONT）和用于ONT检测光传输误差的方法。 ONT与光线路终端（OLT）连接并构成无源光网络（PON），并且包括被配置为向OLT发送光信号的光发射机，被配置为检测光发射机的误差的误差检测器; 以及控制器，被配置为当所述误差检测器检测到所述光发射机的误差时，通过所述光发射机向所述OLT发送错误消息。

公开(公告)号：US20100041201A1

公开(公告)日：2010-02-18

申请号：US12582073

申请日：2009-10-20

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

Abstract translation: 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。