公开(公告)号：US07998858B2

公开(公告)日：2011-08-16

申请号：US11588769

申请日：2006-10-27

Applicant: Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

Inventor： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC: H01L21/4763

CPC classification number: H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Abstract translation: 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US07626190B2

公开(公告)日：2009-12-01

申请号：US11445801

申请日：2006-06-02

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L29/02

CPC classification number: H01L27/2463 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  Y10S977/762 ,  Y10S977/773 ,  Y10S977/932 ,  Y10S977/936

Abstract: A memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”), with a transistor is disclosed. Further, the invention relates to a method for fabricating a memory device. According one embodiment of the invention, a memory device is provided, having at least one nanowire or nanotube or nanofibre access transistor. In one embodiment, the nanowire or nanotube or nanofibre access transistor directly contacts a switching active material of the memory device. According to an additional embodiment, a memory device includes at least one nanowire or nanotube or nanofibre transistor with a vertically arranged nanowire or nanotube or nanofibre.

Abstract translation: 公开了一种存储器件，特别涉及一种具有晶体管的电阻切换存储器件，例如相变随机存取存储器（“PCRAM”）。 此外，本发明涉及一种用于制造存储器件的方法。 根据本发明的一个实施例，提供一种具有至少一个纳米线或纳米管或纳米纤维存取晶体管的存储器件。 在一个实施例中，纳米线或纳米纤维或纳米纤维存取晶体管直接接触存储器件的开关活性材料。 根据另外的实施例，存储器件包括至少一个具有垂直排列的纳米线或纳米管或纳米纤维的纳米线或纳米纤维或纳米纤维。

公开(公告)号：US07420199B2

公开(公告)日：2008-09-02

申请号：US11182022

申请日：2005-07-14

Applicant: Martin Ulrich Gutsche ,  Harald Seidl ,  Franz Kreupl

Inventor： Martin Ulrich Gutsche ,  Harald Seidl ,  Franz Kreupl

IPC: H01L29/02

CPC classification number: B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.

Abstract translation: 存储单元包括在第一电极和第二电极之间包括纳米线，第二电极和相变材料的第一电极。

公开(公告)号：US07316951B2

公开(公告)日：2008-01-08

申请号：US11191461

申请日：2005-07-28

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8234

CPC classification number: H01L28/91 ,  H01L29/66181

Abstract: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side of the silicon substrate (1); depositing a layer (12) made of a metal oxide in the trench (5); carrying out a thermal treatment for selectively reducing the layer (12), a region of the layer (12) that lies below the insulation collar (10) above the silicon substrate (1) being reduced and being converted into a first capacitor electrode layer (15) made of a corresponding metal silicide, and a region of the layer (12) that lies above the insulation collar (10) not being reduced; selectively removing the non-reduced region of the layer (12) that lies above the insulation collar (10); providing a capacitor dielectric layer (18) in the trench (5) above the first capacitor electrode layer (15); and providing a second capacitor electrode layer (20) in the trench (5) above the capacitor dielectric layer (18).

Abstract translation: 本发明提供一种在硅衬底（1）中具有绝缘套环（10）的沟槽电容器的制造方法，其具有以下步骤：在硅衬底（1）中提供沟槽（5）; 在所述上沟槽区域中提供所述绝缘套环（10）直到所述硅衬底（1）的顶侧; 在沟槽（5）中沉积由金属氧化物制成的层（12）; 进行用于选择性地还原层（12）的热处理，位于硅衬底（1）上方的绝缘套环（10）下方的层（12）的区域被还原并被转换成第一电容器电极层 15），并且位于所述绝缘套环（10）上方的所述层（12）的不被还原的区域; 选择性地去除位于绝缘套环（10）上方的层（12）的非还原区域; 在第一电容器电极层（15）上方的沟槽（5）中提供电容器介电层（18）; 以及在电容器介电层（18）上方的沟槽（5）中提供第二电容器电极层（20）。

公开(公告)号：US07303970B2

公开(公告)日：2007-12-04

申请号：US11125654

申请日：2005-05-10

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/20

CPC classification number: H01L28/56 ,  H01L21/022 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

Abstract: The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

Abstract translation: 本发明提供一种电容元件（100）的制造方法，设置有作为电容元件（100）的第一电极层的基板（101），将作为电极层设置的基板（101）进行调理， 层（102）沉积在经调理的基底（101）上，并且第二电极层（104）被施加在所产生的层叠层上，通过热处理改变层堆叠，使得介电层（102）沉积 在调理衬底（101）上形成电介质混合层（105），其上沉积有介电层（102）上的反应层（103），该电介质混合层具有增加的介电常数（k）或增加的热稳定性。

公开(公告)号：US20070111333A1

公开(公告)日：2007-05-17

申请号：US11280864

申请日：2005-11-17

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L21/00 ,  H01L21/336

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.

Abstract translation: 本发明涉及一种用于制造至少一个相变存储器单元的方法。 该方法至少制造导电材料的至少一个第一层状间隔物，其电耦合到存储单元的PCM材料; 在所述第一层状间隔物的顶部上制造至少一个第二层状间隔物，其中所述第二层状间隔物穿过所述PCM材料区域中的所述第一层状间隔物; 部分地去除第一层状间隔物，其中第二层状间隔物用作用于部分去除第一层状间隔物的硬掩模，使得第一层状间隔物形成接触PCM材料区域的至少一个电极。

公开(公告)号：US07195973B2

公开(公告)日：2007-03-27

申请号：US11205323

申请日：2005-08-17

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L29/66181 ,  H01L27/10867

Abstract: The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact The invention likewise provides a corresponding trench capacitor.

Abstract translation: 本发明提供了一种制造具有衬底中的绝缘套环的沟槽电容器的方法，该沟槽电容器在一侧通过埋入触点电连接到衬底，特别是具有平面选择晶体管的半导体存储器单元，该平面选择晶体管设置在 该衬底并经由埋入接头连接。本发明同样提供一种对应的沟槽电容器。

公开(公告)号：US20070052069A1

公开(公告)日：2007-03-08

申请号：US11362384

申请日：2006-02-24

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L29/40 ,  G08B13/14

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated conductor arrangement comprises a substrate with a top side, at least one tubular conductor trench provided in the substrate below the top side of the substrate and a conductor. The conductor comprises at least one tubular conductor layer and is integrated in the conductor trench.

Abstract translation: 集成导体布置包括具有顶侧的基板，设置在基板的下侧的基板中的至少一个管状导体沟槽和导体。 导体包括至少一个管状导体层并且集成在导体沟槽中。

公开(公告)号：US20070037349A1

公开(公告)日：2007-02-15

申请号：US11526788

申请日：2006-09-25

Applicant: Martin Gutsche ,  Harald Seidl ,  Peter Moll

Inventor： Martin Gutsche ,  Harald Seidl ,  Peter Moll

IPC: H01L21/8242

CPC classification number: H01L28/90 ,  H01L27/1085

Abstract: To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of the upwardly extending conductors. The support structure is formed of a material different than the separating material. The separating material can be removed and further processing can be performed on the semiconductor device.

Abstract translation: 为了形成半导体器件，可以形成多个向上延伸的导体。 导体从半导体本体的表面向外延伸，相邻的导体通过分离材料相互分离。 在相邻的向上延伸的导体之间形成至少一个支撑结构。 支撑结构由与分离材料不同的材料形成。 可以去除分离材料并且可以在半导体器件上进行进一步的处理。

公开(公告)号：US07176514B2

公开(公告)日：2007-02-13

申请号：US10413812

申请日：2003-04-15

Applicant: Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

Inventor： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

IPC: H01L27/108 ,  H01L21/76

CPC classification number: H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

Abstract: A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

Abstract translation: 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。