公开(公告)号：US07176514B2

公开(公告)日：2007-02-13

申请号：US10413812

申请日：2003-04-15

申请人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

发明人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

IPC分类号： H01L27/108 ,  H01L21/76

CPC分类号： H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

摘要翻译： 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

公开(公告)号：US07157371B2

公开(公告)日：2007-01-02

申请号：US10653599

申请日：2003-09-02

申请人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

发明人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

IPC分类号： H01L21/44

CPC分类号： H01L27/11502 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28061 ,  H01L21/31138 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/0895 ,  H01L29/4941

摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

摘要翻译： 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。

公开(公告)号：US06953722B2

公开(公告)日：2005-10-11

申请号：US10425461

申请日：2003-04-29

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

IPC分类号： H01L21/311 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L21/31133

摘要： In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

摘要翻译： 在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。 在这种情况下，最初的无定形材料被转化为结晶或多晶形式。 为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。 结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。 通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

公开(公告)号：US06693016B2

公开(公告)日：2004-02-17

申请号：US10233690

申请日：2002-09-03

申请人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

发明人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

IPC分类号： H01L2120

CPC分类号： H01L27/10861

摘要： The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with a material with an increased dielectric constant. An insulation region is formed in the upper wall region of the trench after the first electrode region or the second electrode region has been formed, by selective and local oxidation.

摘要翻译： 新颖的沟槽电容器具有恒定或增加的电容。 第二电极区域的材料和适当的第一电极区域包括金属材料，金属氮化物等，和/或介电区域由介电常数增加的材料形成。 通过选择性和局部氧化，在形成第一电极区域或第二电极区域之后，在沟槽的上壁区域中形成绝缘区域。

公开(公告)号：US20060264054A1

公开(公告)日：2006-11-23

申请号：US11100325

申请日：2005-04-06

申请人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

发明人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

IPC分类号： H01L21/465

CPC分类号： H01L21/30655 ,  H01L21/743 ,  H01L21/76898

摘要： The present invention relates to a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底中的沟槽的方法。 更具体地说，本发明涉及一种蚀刻深沟槽的方法，例如具有30或更高的纵横比的那些。 根据本发明的实施例，用于蚀刻半导体衬底中的沟槽的方法包括第一蚀刻循环，其中沟槽被蚀刻到第一深度。 此后，保护性衬垫至少沉积在沟槽侧壁的上部。 保护性衬垫包括无机材料。 在至少一个第二蚀刻周期期间，将沟槽蚀刻到其最终深度。

公开(公告)号：US07087485B2

公开(公告)日：2006-08-08

申请号：US10765052

申请日：2004-01-28

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

IPC分类号： H01L21/8242

CPC分类号： H01L21/3141 ,  H01L21/31116 ,  H01L27/1087

摘要： A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

摘要翻译： 一种用于在浮雕结构的区域上制造图案化陶瓷层的方法，其中所述层可以布置成基本上垂直于衬底的顶侧。 在示例性实施例中，图案化陶瓷层形成用于沟槽电容器的氧化物环。 氧化物套环由首先在其下部填充有抗蚀剂的沟槽产生，随后在低温ALD方法的帮助下在衬底的未覆盖区域上产生氧化物层。 通过各向异性蚀刻，仅保留布置在沟槽的垂直壁处的陶瓷层的那些部分。 可以随后例如通过氧等离子体去除抗蚀剂填充。

公开(公告)号：US06835417B2

公开(公告)日：2004-12-28

申请号：US10375529

申请日：2003-02-27

申请人： Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

发明人： Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

IPC分类号： C23C1600

CPC分类号： C23C16/45527 ,  C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/481

摘要： The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.

摘要翻译： ALD处理室具有加热辐射源，并且工艺顺序包括在布置在ALD处理室中的衬底的衬底表面上的快速温度变化。 控制温度变化，并通过原位温度步骤优化ALD和CVD工艺，例如为了生产纳米级氨基酸。

公开(公告)号：US20050037565A1

公开(公告)日：2005-02-17

申请号：US10765052

申请日：2004-01-28

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

IPC分类号： C23C16/00 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L21/314 ,  H01L21/70 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L21/3141 ,  H01L21/31116 ,  H01L27/1087

摘要： A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

摘要翻译： 一种用于在浮雕结构的区域上制造图案化陶瓷层的方法，其中所述层可以布置成基本上垂直于衬底的顶侧。 在示例性实施例中，图案化陶瓷层形成用于沟槽电容器的氧化物环。 氧化物套环由首先在其下部填充有抗蚀剂的沟槽产生，随后在低温ALD方法的帮助下在衬底的未覆盖区域上产生氧化物层。 通过各向异性蚀刻，仅保留布置在沟槽的垂直壁处的陶瓷层的那些部分。 可以随后例如通过氧等离子体去除抗蚀剂填充。

公开(公告)号：US09177995B2

公开(公告)日：2015-11-03

申请号：US13591247

申请日：2012-08-22

申请人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

发明人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC分类号： H01L27/10 ,  H01L27/24 ,  H01L21/285 ,  H01L27/108 ,  B82Y10/00 ,  H01L21/768 ,  H01L27/22

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

摘要翻译： 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US07317201B2

公开(公告)日：2008-01-08

申请号：US11296740

申请日：2005-12-07

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

摘要： In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.

摘要翻译： 在制造微电子电极结构体的方法中，制备第一布线面，设置第一布线面上的绝缘区域，形成绝缘区域的贯通孔，形成通孔内的环状电极， 在绝缘区域上形成第二布线平面。 环形电极包括第一侧和第二侧，环形电极在第一侧电连接到第一布线平面，并且第二布线平面电连接到环形电极的第二侧。