公开(公告)号：US20060066364A1

公开(公告)日：2006-03-30

申请号：US11225915

申请日：2005-09-13

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

IPC分类号： H03B1/00

CPC分类号： H03F3/45

摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

公开(公告)号：US06768393B2

公开(公告)日：2004-07-27

申请号：US10271455

申请日：2002-10-16

申请人： Ho-Young Song

发明人： Ho-Young Song

IPC分类号： H03H1100

CPC分类号： H04L25/0298

摘要： A circuit and method for calibrating an active termination resistor irrespective of changes in process, voltage, or temperature is provided. The method includes the steps of (a) calibrating a first variable resistor to have the same resistance as that of an external resistor; (b) at the same time calibrating a second variable resistor to have the same resistance as that of the first variable resistor; and (c) calibrating the active termination resistor to have the same resistance as that of the external resistor. The step of calibrating the first variable resistor to have the same resistance as that of the external resistor is in response to a first control code, and at the same time the step of calibrating the second variable resistor to have the same resistance as that of the first variable resistor is in response to a second control code. The first control code is generated to correspond to a comparison value in resistance of the first variable resistor with the external resistor, and the second control code is generated to correspond to a comparison value in resistance of the first variable resistor with the second variable resistor. During step (a), the resistance of the first variable resistor and the resistance of the second variable resistor increase or decrease at the same time.

摘要翻译： 提供了用于校准有源终端电阻器而不考虑过程，电压或温度变化的电路和方法。 该方法包括以下步骤：（a）校准第一可变电阻器以具有与外部电阻器相同的电阻; （b）同时校准第二可变电阻器以具有与第一可变电阻器相同的电阻; 和（c）校准有源终端电阻以具有与外部电阻器相同的电阻。 将第一可变电阻器校准为具有与外部电阻器相同的电阻的步骤是响应于第一控制代码，并且同时将第二可变电阻器校准为具有与第二可变电阻器相同的电阻的步骤 第一可变电阻器响应于第二控制码。 产生第一控制代码以对应于第一可变电阻器与外部电阻器的电阻的比较值，并且产生第二控制代码以对应于第一可变电阻器与第二可变电阻器的电阻的比较值。 在步骤（a）期间，第一可变电阻器的电阻和第二可变电阻器的电阻同时增加或减小。

公开(公告)号：US06734707B2

公开(公告)日：2004-05-11

申请号：US10340831

申请日：2003-01-13

申请人： Ho-young Song ,  Kyu-hyoun Kim ,  Su-bong Jang

发明人： Ho-young Song ,  Kyu-hyoun Kim ,  Su-bong Jang

IPC分类号： H03M700

CPC分类号： G11C7/1093 ,  G11C7/1072 ,  G11C7/1087 ,  G11C2207/105 ,  G11C2207/108

摘要： A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer. Use of the data input circuit makes a load on a reference clock the same or substantially the same as that on each group of data. Therefore, a load difference between the reference clock and each group of data is reduced to reduce a skew therebetween.

摘要翻译： 一种用于半导体器件的数据输入电路，所述数据输入电路减小了获取信号与多组数据之间的负载差异。 数据输入电路包括第一到第N个锁存单元，用于分别响应于参考时钟（N是大于2的自然数）来锁存N组数据中的每一个，以及用于发送参考时钟和 N组数据到第一至第N个锁存单元。 每个第一至第N个锁存单元包括用于缓冲参考时钟的时钟缓冲器; 数据缓冲器，用于缓冲N组数据的相应的数据组; N-1个虚拟元素，用于分别接收N组数据中的每一个，除了输入到数据缓冲器的数据组之外; 以及用于锁存从数据缓冲器输出的数据与从时钟缓冲器输出的信号同步的锁存器。 使用数据输入电路使参考时钟上的负载与每组数据上的相同或基本相同。 因此，参考时钟与每组数据之间的负载差减小，以减少它们之间的偏斜。

公开(公告)号：US06707759B2

公开(公告)日：2004-03-16

申请号：US10283124

申请日：2002-10-30

申请人： Ho-young Song

发明人： Ho-young Song

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2281

摘要： The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates a plurality of transfer signals with a plurality of sampling signals based on a CAS latency to create a desired timing relationship between each sampling signal and the associated transfer signal. The latency circuit stores read information in accordance with at least one of the plurality of sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

摘要翻译： 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间来选择性地将多个传送信号与多个采样信号相关联，以在每个采样信号和相关联的传送信号之间产生期望的定时关系。 延迟电路根据多个采样信号中的至少一个存储读取信息，并且基于与用于存储所读取的信息的采样信号相关联的传送信号产生等待时间信号。

公开(公告)号：US06545918B2

公开(公告)日：2003-04-08

申请号：US09878112

申请日：2001-06-08

申请人： Ho-young Song

发明人： Ho-young Song

IPC分类号： G11C700

CPC分类号： G11C11/4074 ,  G11C5/145

摘要： A semiconductor memory device having a boosted voltage stabilization circuit includes a plurality of memory cell array blocks sharing a predetermined circuit that is operable to use a boosted voltage higher than a power supply voltage. The device also includes a voltage stabilization circuit comprising an additional load for being charged with the boosted voltage when a memory cell array block at an edge of the cell array is selected. Accordingly, the boosted voltage stabilization circuit enables the semiconductor memory device to use a uniform single boosted voltage level regardless of the location of the selected cell array block, thereby preventing the reduction in the life span of the device or the deterioration in the operating characteristics of the device that is normally caused by excessive increases in the boosted voltage level.

摘要翻译： 具有升压稳定电路的半导体存储器件包括共享预定电路的多个存储单元阵列块，其可操作以使用高于电源电压的升压电压。 该装置还包括电压稳定电路，该电压稳定电路包括当选择在单元阵列的边缘处的存储单元阵列块时用于对升高的电压进行充电的附加负载。 因此，升压型电压稳定电路能够使半导体存储器件与所选择的单元阵列块的位置无关地使用均匀的单一提升电压电平，从而防止器件寿命的降低或者操作特性的劣化 该器件通常由升压电压电平的过度增加引起。

公开(公告)号：US09087613B2

公开(公告)日：2015-07-21

申请号：US13753165

申请日：2013-01-29

申请人： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

发明人： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC分类号： G11C29/00 ,  G11C29/44 ,  G06F11/27 ,  G06F11/20 ,  G11C29/56 ,  G01R31/3187 ,  G11B20/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02

CPC分类号： G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

摘要翻译： 提供了一种用于修复存储器测试系统中的存储单元的方法和装置。 测试设备通过根据测试命令测试存储设备来检测故障地址，并将故障地址临时存储在故障地址存储器（FAM）中。 故障地址根据故障地址传输模式发送到存储设备，被临时存储在存储器件的暂时失效地址存储器中，然后存储在作为非易失性存储设备的反熔丝阵列 。 为了确保数据的可靠性，可以读取存储的数据以验证数据，并且验证结果可以与测试设备串联或并行传输。

公开(公告)号：US09006973B2

公开(公告)日：2015-04-14

申请号：US13229152

申请日：2011-09-09

申请人： Ho Young Song

发明人： Ho Young Song

IPC分类号： H05B37/02 ,  H01L25/16 ,  H01L33/48

CPC分类号： H01L25/167 ,  H01L33/486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light emitting device includes: a substrate having opposed first and second main faces; a light emitting element mounted on the first main face of the substrate; and a driver integrated circuit (IC) formed in an area corresponding to a lower side of the light emitting element within the substrate, and adjusting the amount of current applied to the light emitting element. Since the circuit provided to drive a light emitting diode (LED) is integrated within the substrate, a compact light emitting device having an integrated structure can be obtained.

摘要翻译： 发光器件包括：具有相对的第一和第二主面的衬底; 安装在所述基板的所述第一主面上的发光元件; 以及形成在与基板内的发光元件的下侧对应的区域中的驱动器集成电路（IC），并且调整施加到发光元件的电流量。 由于设置用于驱动发光二极管（LED）的电路集成在基板内，因此可以获得具有集成结构的紧凑型发光装置。

公开(公告)号：US08797898B2

公开(公告)日：2014-08-05

申请号：US13333544

申请日：2011-12-21

申请人： Tae-Yeon Kim ,  Ho-Young Song

发明人： Tae-Yeon Kim ,  Ho-Young Song

IPC分类号： H01R31/08 ,  H04W8/26 ,  H04L29/06 ,  H04L12/24

CPC分类号： H04W8/26 ,  H04L41/5067 ,  H04L63/08

摘要： An open wireless access network apparatus includes an Internet protocol (IP) resource management unit to allocate IPs, respectively, to a plurality of provider servers and open wireless access points (APs), and map the IP of each provider server to the IP of each open wireless AP; a subscriber movement management unit to provide a second wireless AP with an IP that has been allocated to a first wireless AP when a mobile device changes from one area in which the mobile device has a signal delivered from the first wireless AP to another area in which the mobile device has a signal delivered from the second wireless AP; and a wireless AP connection control unit to allow the mobile device to be connected to the second wireless AP through the allocated IP.

摘要翻译： 开放式无线接入网络装置包括分别向多个提供商服务器和开放无线接入点（AP）分配IP的因特网协议（IP）资源管理单元，并将每个提供者服务器的IP映射到每个 开放无线AP; 用户移动管理单元，用于当移动设备从移动设备具有从第一无线AP传递的信号的一个区域改变到另一个区域时，向第二无线AP提供已被分配给第一无线AP的IP，其中， 移动设备具有从第二无线AP传递的信号; 以及无线AP连接控制单元，其允许移动设备通过所分配的IP连接到第二无线AP。

公开(公告)号：US08780924B2

公开(公告)日：2014-07-15

申请号：US13301445

申请日：2011-11-21

申请人： Sun Me Kim ,  Ho Young Song

发明人： Sun Me Kim ,  Ho Young Song

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L45/50 ,  H04L12/462 ,  H04L45/00 ,  H04L45/04 ,  H04L45/52 ,  H04L47/724 ,  H04L47/785

摘要： A generalized multiprotocol label switching (GMPLS) non-enabled network gateway for routing between a GMPLS enabled network and a GMPLS non-enabled network for connection between the GMPLS enabled network and the GMPLS non-enabled network, and an operating method for the GMPLS non-enabled network gateway are provided. The GMPLS non-enabled network gateway may include a border gateway protocol (BGP) routing unit to exchange routing information between a first GMPLS enabled network and a third GMPLS enabled network using a BGP, and a resource reservation protocol signaling unit to search for a path to another network using the routing information and to perform inter-autonomous system (AS) signaling by including a control plane of the first GMPLS enabled network or the third GMPLS enabled network and a signaling interface applying an out-of-band method.

摘要翻译： 一种通用多协议标签交换（GMPLS）非启用网络网关，用于在启用GMPLS的网络和GMPLS非启用网络之间进行路由，用于启用GMPLS的网络和GMPLS未启用网络之间的连接，以及GMPLS非启用网络的操作方法 提供了启用的网关。 GMPLS非启用网关可以包括边界网关协议（BGP）路由单元，用于使用BGP在第一启用GMPLS的网络和启用第三GMPLS的网络之间交换路由信息，以及资源预留协议信令单元来搜索路径 使用路由信息到另一个网络，并且通过包括启用第一GMPLS的网络或启用第三GMPLS的网络的控制平面以及应用带外方法的信令接口来执行自治系统（AS）信令。

公开(公告)号：US08637667B2

公开(公告)日：2014-01-28

申请号：US13382265

申请日：2010-07-07

申请人： Young Lag Cho ,  Jong Un Cho ,  Sung Yoon Baek ,  Ho Young Song ,  Tae Kyo Park ,  Sung Ho Woo ,  Yong Zu Kim

发明人： Young Lag Cho ,  Jong Un Cho ,  Sung Yoon Baek ,  Ho Young Song ,  Tae Kyo Park ,  Sung Ho Woo ,  Yong Zu Kim

IPC分类号： C07D413/02 ,  C07D413/04 ,  C07D273/04

CPC分类号： C07D413/14 ,  C07D413/12

摘要： Provided is a method for preparing (S)-5-chloro-N-((3-(4-(5,6-dihydro-4H-1,2,4-oxadiazin-3-yl)phenyl)-2-oxooxazolidin-5-yl)methyl)thiophene-2-carboxamide derivatives of Formula (I) which are useful as blood coagulation factor Xa inhibitors, and said method using 1-fluoro-4-nitrobenzen as a starting material. According to the method of the present invention, (S)-5-chloro-N-((3-(4-(5,6-dihydro-4H-1,2,4-oxadiazin-3-yl)phenyl)-2-oxooxazolidin-5-yl)methyl)thiophene-2-carboxamide derivatives of Formula (I) which are useful as blood coagulation factor Xa inhibitors can be prepared in a high purity and a high yield.

摘要翻译： 提供制备（S）-5-氯-N - （（3-（4-（5,6-二氢-4H-1,2,4-恶二嗪-3-基）苯基）-2-氧代恶唑烷 -5-基）甲基）噻吩-2-甲酰胺衍生物，所述方法使用1-氟-4-硝基苯作为原料，所述方法可用作凝血因子Xa抑制剂。 根据本发明的方法，（S）-5-氯-N - （（3-（4-（5,6-二氢-4H-1,2,4-恶二嗪-3-基）苯基） - 可用作凝血因子Xa抑制剂的式（I）的噻吩-2-甲酰胺衍生物可以以高纯度和高产率制备。