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75 条记录 (耗时 0.015 秒)

    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted
    72.
    发明申请
    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted 失效
    堆叠的片上芯片封装，具有镜像结构和双列直插存储器模块，其上安装有堆叠的片上芯片封装

    公开(公告)号：US20060055017A1

    公开(公告)日：2006-03-16

    申请号：US11177736

    申请日：2005-07-08

    申请人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    发明人： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    IPC分类号： H01L23/02

    CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00014

    摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

    摘要翻译： 本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。 第一半导体芯片的底面朝向第二半导体芯片的底面。 插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。 通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。 由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。 因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

    Mounting structure in integrated circuit module
    74.
    发明申请
    Mounting structure in integrated circuit module 失效
    集成电路模块中的安装结构

    公开(公告)号：US20050104206A1

    公开(公告)日：2005-05-19

    申请号：US10988390

    申请日：2004-11-12

    申请人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

    发明人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

    IPC分类号： H01L25/10 ,  G11C5/00 ,  H01L21/50 ,  H01L23/48 ,  H01L25/18 ,  H05K1/18

    CPC分类号： H05K1/181 ,  H01L2924/0002 ,  H05K2201/097 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

    摘要： Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.

    摘要翻译： 本发明的实施例可以包括用于高密度安装的集成电路模块结构。 一个实施例可以包括布线​​板，具有在其至少一个表面上具有沿第一方向确定的安装长度的安装长度和在第二方向上确定的安装宽度的安装空间以及具有封装安装组合的多个集成电路封装 长度比布线板的安装长度长。 实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。 本实施例可以具有水平和垂直地彼此重叠的封装。 即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

    Circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof
    75.
    发明授权
    Circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof 有权
    用于控制半导体存储器件的AC定时参数的电路及其方法

    公开(公告)号：US06795354B2

    公开(公告)日：2004-09-21

    申请号：US10321242

    申请日：2002-12-16

    申请人： Jeong-Hyeon Cho ,  Byung-Chul Kim

    发明人： Jeong-Hyeon Cho ,  Byung-Chul Kim

    IPC分类号： G11C11063

    CPC分类号： G11C7/222 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/2254

    摘要： A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.

    摘要翻译： 提供一种用于控制半导体存储器件的AC定时参数的电路及其方法。 AC定时参数控制电路包括延迟时间定义部分，比较部分和控制部分。 控制电路将输入信号的脉冲宽度或周期与由延迟时间限定部分设定的基准宽度和由比较部分生成的参考脉冲的一个或多个不同参考宽度脉冲进行比较。 控制部分指示输入信号宽度或周期是否小于或大于参考宽度脉冲。 控制电路输出信号可以用于基于AC定时参数与一个或多个参考值的直接比较来定制设备的操作。