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    Analog to digital converter
    76.
    发明申请
    Analog to digital converter 失效
    模数转换器

    公开(公告)号：US20050012651A1

    公开(公告)日：2005-01-20

    申请号：US10919213

    申请日：2004-08-16

    Applicant: Klaas Bult ,  Aaron Buchwald

    Inventor： Klaas Bult ,  Aaron Buchwald

    IPC: H03M1/06 ,  H03M1/36 ,  H03M1/34

    CPC classification number: H03M1/0646 ,  H03M1/36

    Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

    Abstract translation: 提供了一种用于减少模数转换器中连续的单元格对的输出之间的不匹配的电路。 电压输入装置耦合到每个单元的第一输入端以引入和输入电压。 参考电压装置耦合到每个单元的第二输入端子以引入参考电压的渐进分数。 低阻抗装置耦合在相应的第一输出端子之间，并连接在连续的电池中的相应的第二输出端子之间，以将负载电流牵引到连续的电池，影响相对电压，从而减少电池错配对这些输出端子的影响。 最后，高阻抗装置耦合到连续单元中的每个第一输出端和每个第二输出端。

    Digital to analog converter with reduced ringing
    79.
    发明授权
    Digital to analog converter with reduced ringing 有权

    公开(公告)号：US06414618B1

    公开(公告)日：2002-07-02

    申请号：US09909282

    申请日：2001-07-19

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M166

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Digital to analog converter with reduced ringing
    80.
    发明授权
    Digital to analog converter with reduced ringing 有权
    数模转换器减少振铃

    公开(公告)号：US06191719B1

    公开(公告)日：2001-02-20

    申请号：US09458331

    申请日：1999-12-10

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M166

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

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