中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8570 records (took 0.033 seconds)

    KEY UPDATE MANAGEMENT SYSTEM AND KEY UPDATE MANAGEMENT METHOD
    71.
    发明公开
    KEY UPDATE MANAGEMENT SYSTEM AND KEY UPDATE MANAGEMENT METHOD 审中-公开

    公开(公告)号：US20240089097A1

    公开(公告)日：2024-03-14

    申请号：US17941515

    申请日：2022-09-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takahiko SUGAHARA ,  Yuichi IWAYA ,  Akira HAMAGUCHI

    IPC: H04L9/08 ,  H04L9/14 ,  H04L9/32

    CPC classification number: H04L9/0891 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3226

    Abstract: When the external storage itself is replaced by a legitimate old key by a malicious third party, the security IP cannot recognize that it is the old key and can be easily rolled back, that is, the old key is regarded as the legitimate key and operates. An OTP is provided in the SoC, and the version of the key ring is managed in one control table area. Specifically, predetermined information that is updated in synchronization with the key update is written in the management table area of the OTP, and an authentication value is calculated by associating the predetermined information with a key ring including the update key. The calculated authentication value is added and registered when registering the key ring.

    SEMICONDUCTOR DEVICE
    72.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240088238A1

    公开(公告)日：2024-03-14

    申请号：US18330660

    申请日：2023-06-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Satoru TOKUDA

    IPC: H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/408 ,  H01L29/407 ,  H01L29/7813

    Abstract: A semiconductor device includes a trench formed in an n-type semiconductor substrate, a p-type body region, an n-type source region, a field plate electrode formed at a lower portion of the trench, and a gate electrode formed at an upper portion of the trench. A gate potential is to be supplied to the gate electrode, a source potential is to be supplied to the source region and the body region, and a drain potential is to be supplied to the semiconductor substrate. A potential larger than the source potential and smaller than the drain potential is to be supplied to the field plate electrode.

    SEMICONDUCTOR DEVICE
    75.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240038888A1

    公开(公告)日：2024-02-01

    申请号：US18334763

    申请日：2023-06-14

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06

    CPC classification number: H01L29/7817 ,  H01L27/088 ,  H01L29/0615

    Abstract: A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.

    Method of manufacturing semiconductor device
    76.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US11882697B2

    公开(公告)日：2024-01-23

    申请号：US17697380

    申请日：2022-03-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shu Shimizu

    IPC: H01L29/788 ,  H01L27/06 ,  H01L21/70 ,  H10B41/42 ,  H01L29/66

    CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

    Data processing apparatus and memory protection method
    79.
    发明授权
    Data processing apparatus and memory protection method 有权

    公开(公告)号：US11868277B2

    公开(公告)日：2024-01-09

    申请号：US17559113

    申请日：2021-12-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasuhiro Sugita

    IPC: G06F12/14 ,  G06F12/0866

    CPC classification number: G06F12/145 ,  G06F12/0866 ,  G06F12/1458 ,  G06F2212/152

    Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.

Patent Agency Ranking