公开(公告)号：US07932143B1

公开(公告)日：2011-04-26

申请号：US12604281

申请日：2009-10-22

Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

IPC: H01L21/8238

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：US07767534B2

公开(公告)日：2010-08-03

申请号：US12240682

申请日：2008-09-29

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L29/66636

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，沉积覆盖栅电极的应力诱导层，退火含硅衬底以重结晶 栅电极，去除应力诱导层，使用栅电极作为蚀刻掩模蚀刻到衬底中的凹槽，以及在凹槽中外延生长杂质掺杂的含硅区域。

公开(公告)号：US20100109056A1

公开(公告)日：2010-05-06

申请号：US12330292

申请日：2008-12-08

Applicant: Rohit PAL ,  Man Fai NG ,  David BROWN

Inventor： Rohit PAL ,  Man Fai NG ,  David BROWN

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

公开(公告)号：US20100096698A1

公开(公告)日：2010-04-22

申请号：US12644882

申请日：2009-12-22

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer

Abstract translation: 提供了应力增强型MOS晶体管。 提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。 绝缘体上半导体结构包括：衬底，半导体层和设置在衬底和半导体层之间的绝缘层。 半导体层具有第一表面，第二表面和第一区域。 栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

公开(公告)号：US20100055394A1

公开(公告)日：2010-03-04

申请号：US12551071

申请日：2009-08-31

Applicant: Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

Inventor： Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

IPC: B32B3/10 ,  B32B37/06

CPC classification number: F16K99/0032 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/50273 ,  B01L3/502738 ,  B01L3/502746 ,  B01L2300/0819 ,  B01L2400/0481 ,  B01L2400/0655 ,  B01L2400/0677 ,  F15B15/10 ,  F16K99/0044 ,  Y10T137/0391 ,  Y10T137/1624 ,  Y10T137/1812 ,  Y10T137/2142 ,  Y10T137/218 ,  Y10T137/2191 ,  Y10T137/2196 ,  Y10T137/2202 ,  Y10T137/2218 ,  Y10T428/23 ,  Y10T428/234 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24612

Abstract: A microactuator may be configured by activating a source of electromagnetic radiation to heat and melt a selected set of phase-change plugs embedded in a substrate of the microactuator, pressurizing a common pressure chamber adjacent to each of the plugs to deform the melted plugs, and deactivating the source of electromagnetic radiation to cool and solidify the melted plugs.

Abstract translation: 微致动器可以通过激活电磁辐射源来加热和熔化嵌入在微致动器的衬底中的一组相变插塞，对与每个插塞相邻的公共压力室进行加压以使熔化的插头变形，以及 停用电磁辐射源以冷却和固化熔化的塞子。

公开(公告)号：US20090280627A1

公开(公告)日：2009-11-12

申请号：US12119384

申请日：2008-05-12

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

IPC: H01L21/322

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract translation: 提供一种制造半导体晶体管器件的方法。 制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。 然后，围绕栅极结构的侧壁形成间隔物。 接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。 在该步骤中，栅极结构和间隔物用作离子注入掩模。 离子在半导体材料中形成非晶化区域。 此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。 此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

公开(公告)号：US20090228132A1

公开(公告)日：2009-09-10

申请号：US12045081

申请日：2008-03-10

Applicant: Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

Inventor： Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

IPC: G06F17/00

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method includes receiving a performance distribution for a plurality of devices to be fabricated in a semiconductor process flow. A performance target for a particular device is specified based on the performance distribution. A stressed material is formed in a recess adjacent a gate electrode of a transistor in the particular device in accordance with at least one operating recipe. The recess is spaced from the gate electrode by a gate proximity distance. A target value for the gate proximity distance is determined based on the performance target. At least one parameter of the operating recipe is determined based on the target value for the gate proximity distance.

Abstract translation: 一种方法包括接收要在半导体工艺流程中制造的多个器件的性能分布。 基于性能分布指定特定设备的性能目标。 根据至少一个操作配方，在与特定装置中的晶体管的栅电极相邻的凹部中形成应力材料。 凹槽与栅电极隔开一个栅极接近距离。 基于性能目标确定门接近距离的目标值。 基于门接近距离的目标值确定操作配方的至少一个参数。

公开(公告)号：US20090176356A1

公开(公告)日：2009-07-09

申请号：US11971481

申请日：2008-01-09

Applicant: Rohit PAL ,  Jon KLUTH ,  David BROWN

Inventor： Rohit PAL ,  Jon KLUTH ,  David BROWN

IPC: H01L21/22

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/7848

Abstract: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region.

Abstract translation: 提供了使用热梯度诱导膜制造半导体器件的方法。 一种方法包括提供具有第一区域和第二区域的衬底，并形成覆盖第二区域并暴露第一区域的膜。 对衬底进行热处理，其中膜在第一区域和第二区域之间引起预定的热梯度。

公开(公告)号：US07534689B2

公开(公告)日：2009-05-19

申请号：US11562209

申请日：2006-11-21

Applicant: Rohit Pal ,  Igor Peidous ,  David Brown

Inventor： Rohit Pal ,  Igor Peidous ,  David Brown

IPC: H01L21/20

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。

公开(公告)号：US20080237811A1

公开(公告)日：2008-10-02

申请号：US11694057

申请日：2007-03-30

Applicant: Rohit Pal ,  David F. Brown

Inventor： Rohit Pal ,  David F. Brown

IPC: H01L23/544

CPC classification number: H01L22/20

Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.

Abstract translation: 用于捕获工艺历史的方法包括至少执行用于在半导体衬底上形成特征的第一工艺。 在执行第一处理之后，在半导体基板的第一区域上形成第一盖。 执行至少第二过程，用于在除了第一区域之外的第二区域中形成特征，同时将第一盖留在适当位置，从而防止第一盖子覆盖的第一区域中的特征暴露于第二过程。 在第一区域中测量第一特征的第一特征，并且测量第二区域中的第二特征的第二特征。 晶片包括设置在第一区域中的第一部分完成特征。 在第一部分完成的特征之上形成第一盖。 第二部分完成的特征被布置在不同于第一区域的晶片的第二区域中。 第二部分完成的功能处于完成的后期，而不是第一部分完成的功能。