公开(公告)号：US20240204643A1

公开(公告)日：2024-06-20

申请号：US18068579

申请日：2022-12-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Alessandro ZAFARANA ,  Salvatore LEONE

IPC: H02M1/00 ,  H02M3/158

CPC classification number: H02M1/0009 ,  H02M3/158

Abstract: Current sensing in switching power converters. At least one example is a method comprising: discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle; providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode; charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode; and providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode.

公开(公告)号：US20240203846A1

公开(公告)日：2024-06-20

申请号：US18595569

申请日：2024-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20240186218A1

公开(公告)日：2024-06-06

申请号：US18491369

申请日：2023-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Jihwan KIM ,  Dongwook KANG

IPC: H01L23/433 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3672 ,  H01L23/49822 ,  H01L25/0652

Abstract: In a general aspect, a semiconductor device module includes a ceramic substrate having a first surface and a second surface opposite the first surface. A patterned metal layer is disposed on the first surface of the ceramic substrate, and a semiconductor die is disposed on the patterned metal layer. A cooling structure is disposed on the second surface of the ceramic substrate, where the cooling structure includes a plurality of fluidic-cooling channels. The module also includes a molding compound that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die, and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

公开(公告)号：US20240178269A1

公开(公告)日：2024-05-30

申请号：US18058915

申请日：2022-11-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jimmy Robert Hannes FRANCHI ,  Martin DOMEIJ

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

公开(公告)号：US11996036B2

公开(公告)日：2024-05-28

申请号：US17706139

申请日：2022-03-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Gerard Ruttens ,  Manuel Hortensia L. Meyers

IPC: G09G3/20 ,  G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0286 ,  G09G2380/10

Abstract: A method includes transmitting a plurality of signal frames from a master device over a serial communication bus at a constant rate to a first slave device from a set of slave devices. The set of slave devices and the master device are connected in series within a master-slave communication ring. The first slave device is coupled to at least one light source. The method further includes transmitting the plurality of signal frames from the first slave device to a second slave device from the set of slave devices.

公开(公告)号：US11994411B2

公开(公告)日：2024-05-28

申请号：US17652535

申请日：2022-02-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jacques Jean Bertin

IPC: G01D18/00 ,  G01D5/22 ,  G01D5/245

CPC classification number: G01D18/001 ,  G01D5/22 ,  G01D5/2452 ,  G01D5/2455 ,  G01D5/2458

Abstract: A vernier sensor including a coarse sensor and a fine sensor may require calibration to ensure accurate position measurements. Calibration may include determining coefficients for harmonics that can be added to the coarse sensor output and the fine sensor output to reduce harmonic distortion. The disclosure describes using the offset and variance of a difference signal as the basis for calibration. This approach is possible at least because the frequencies of the coarse sensor and fine sensor can be selected to reduce the complexity of these calculations.

公开(公告)号：US20240170378A1

公开(公告)日：2024-05-23

申请号：US18056442

申请日：2022-11-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Heejo CHI ,  Seungwon IM ,  Oseob JEON

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48175 ,  H01L2224/48225 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/186

Abstract: A module includes an assembly of a semiconductor device die, a lead frame connected to the semiconductor device die, and a substrate connected to the lead frame. The substrate includes at least one plated-through hole (PTH). A mold body encapsulates the assembly. The mold body includes a through-mold via (TMV) aligned with a portion of the substrate including the at least one PTH. The PTH is exposed in the TMV to an environment outside the mold body and is physically accessible from outside the mold body through the TMV.

公开(公告)号：US20240169586A1

公开(公告)日：2024-05-23

申请号：US18057408

申请日：2022-11-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Nicholas Paul COWLEY ,  Mukesh Rao ENGLA SYAM

IPC: G06T7/80

CPC classification number: G06T7/80

Abstract: An image sensor may include a pixel array and associated readout paths calibration circuitry. The image sensor may include first column readout circuits formed along a first edge of the pixel array and second column readout circuits formed along a second opposing edge of the pixel array. The readout paths calibration circuitry may include one or more first calibration readout circuits located by the first edge of the array, one or more second calibration readout circuits located by the second edge of the array, and an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits and the one or more second calibration readout circuits. The one or more second calibration readout circuits and the second column readout circuits can receive a reference voltage that is dynamically adjusted based on the error signal.

公开(公告)号：US11984388B2

公开(公告)日：2024-05-14

申请号：US18330133

申请日：2023-06-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen St. Germain ,  Jay A. Yoder ,  Dennis Lee Conner ,  Frank Robert Cervantes ,  Andrew Celaya

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49805 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/181

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

公开(公告)号：US11982776B2

公开(公告)日：2024-05-14

申请号：US17522019

申请日：2021-11-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Marek Hustava ,  Jiri Kantor ,  Tomas Suchy

IPC: G01S7/52 ,  G01S7/526 ,  G01S15/931

CPC classification number: G01S7/52006 ,  G01S7/526 ,  G01S15/931

Abstract: Disclosed sensors, sensor controllers, and sensor control methods enhance transducer performance using a model-based equalization method that can be performed in the field. One illustrative method for operating a piezoelectric-based sensor includes: sensing a response of a piezoelectric transducer as a function of frequency; deriving parameter values of an equivalent circuit for the piezoelectric transducer from the response; using a squared magnitude of the equivalent circuit's transfer function to determine a system level selectivity; and adapting at least one operating parameter of the sensor based on the system level selectivity. One illustrative controller for a piezoelectric transducer includes: a transmitter that drives the piezoelectric transducer; a receiver that senses a response of the piezoelectric transducer; and a processing circuit coupled to the transmitter and to the receiver to calibrate the transducer using the foregoing method.