公开(公告)号：US11996397B2

公开(公告)日：2024-05-28

申请号：US17360925

申请日：2021-06-28

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David Gani

IPC: H01L25/16 ,  G01S17/04 ,  H01L21/768 ,  H01L23/48 ,  H01L31/02 ,  H01L31/167 ,  H01L31/18 ,  H01S5/02325 ,  H04M1/02

CPC classification number: H01L25/167 ,  G01S17/04 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005 ,  H01L31/167 ,  H01L31/1804 ,  H01L31/186 ,  H01S5/02325 ,  H04M1/026 ,  G06F2203/04105

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

公开(公告)号：US11908831B2

公开(公告)日：2024-02-20

申请号：US17483076

申请日：2021-09-23

Applicant: STMicroelectronics PTE LTD

Inventor： Chun Yi Teng ,  David Gani

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/95 ,  H01L21/768 ,  H01L21/78 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/11849 ,  H01L2224/95001

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

公开(公告)号：US20240036019A1

公开(公告)日：2024-02-01

申请号：US18485072

申请日：2023-10-11

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

Inventor： Malek BRAHEM ,  Hatem MAJERI ,  Olivier LE NEEL ,  Ravi SHANKAR ,  Enrico Rosario ALESSI ,  Pasquale BIANCOLILLO

IPC: G01N33/00 ,  G01N27/12 ,  G01N27/02

CPC classification number: G01N33/0047 ,  G01N27/12 ,  G01N27/021

Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.

公开(公告)号：US11742437B2

公开(公告)日：2023-08-29

申请号：US17187510

申请日：2021-02-26

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David Gani ,  Yiying Kuo

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/02 ,  H01L21/78

CPC classification number: H01L31/0203 ,  H01L21/78 ,  H01L31/02002 ,  H01L31/02005 ,  H01L31/0392 ,  H01L31/1876 ,  H01L31/1896

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.

公开(公告)号：US20230236161A1

公开(公告)日：2023-07-27

申请号：US18091470

申请日：2022-12-30

Applicant: STMicroelectronics PTE LTD ,  STMicroelectronics S.r.l.

Inventor： Ravi SHANKAR ,  Wei Ren Douglas LEE ,  Giuseppe BRUNO

IPC: G01N33/00 ,  G01N27/04

CPC classification number: G01N33/0027 ,  G01N27/045

Abstract: A gas sensor is formed by a thin-film semiconductor metal-oxide gas sensing layer, with a thermally conductive and electrically-insulating layer in direct physical contact with a back of the gas sensing layer to carry the gas sensing layer. Sensing circuitry applies a voltage to the gas sensing layer and measures a current flowing through the gas sensing layer. The current flowing through the gas sensing layer is indicative of whether a gas under detection has been detected by the gas sensing layer, and serves to self-heat the gas sensing layer. A support structure extends from a substrate to make direct physical contact with and carry the thermally conductive and electrically insulating layer about a perimeter of a back face thereof, with the support structure shaped to form an air gap between the back of the thermally conductive and electrically insulating layer and a front of the substrate.

公开(公告)号：US20230197688A1

公开(公告)日：2023-06-22

申请号：US18166931

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L21/565 ,  H01L21/563 ,  H01L23/49866 ,  H01L25/16 ,  H01L23/13 ,  H01L24/32 ,  H01L23/49816 ,  H01L2224/05009 ,  H01L2225/06503 ,  H01L2224/32225

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US11581280B2

公开(公告)日：2023-02-14

申请号：US17104968

申请日：2020-11-25

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David Gani

IPC: H01L23/00 ,  H01L23/498

Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

公开(公告)号：US20230032887A1

公开(公告)日：2023-02-02

申请号：US17860491

申请日：2022-07-08

Applicant: STMicroelectronics Pte Ltd

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16

Abstract: Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.

公开(公告)号：US11562937B2

公开(公告)日：2023-01-24

申请号：US17145028

申请日：2021-01-08

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yun Liu ,  David Gani

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/28

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

公开(公告)号：US11502192B2

公开(公告)日：2022-11-15

申请号：US17217689

申请日：2021-03-30

Applicant: STMicroelectronics Pte Ltd

Inventor： Shin Phay Lee ,  Voon Cheng Ngwan ,  Maurizio Gabriele Castorina

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L27/07 ,  H01L29/06 ,  H01L29/861 ,  H01L27/24

Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.