公开(公告)号：US20230359801A1

公开(公告)日：2023-11-09

申请号：US17662037

申请日：2022-05-04

Applicant: Xilinx, Inc.

Inventor： Sreesan Venkatakrishnan ,  Nitin Deshmukh ,  Satish B. Sivaswamy

IPC: G06F30/394 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/398 ,  G06F2111/04

Abstract: Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection may be performed on the graph. For each cycle detected on the graph, the cycle may be broken by deleting the edge from the graph and ripping-up a portion of the routing solution corresponding to the deleted edge. The circuit design, or portion thereof, for which the routing solution was ripped up may be re-routed using an increased cost for a shared routing resource freed from the ripping-up.

公开(公告)号：US20230325333A1

公开(公告)日：2023-10-12

申请号：US18206045

申请日：2023-06-05

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F13/40 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F9/30043 ,  G06F13/1663 ,  G06F13/1668 ,  G06F2209/5011 ,  G06F2213/0038

Abstract: An integrated circuit (IC) for adaptive memory expansion scheme is proposed, which comprises: a home agent comprising a first memory expansion pool and a second memory expansion pool; a first port connecting the home agent to a first memory expansion device, where the first memory expansion device comprises a first memory pool; a second port connecting the home agent to a second memory expansion device, where the second memory expansion device comprises a second memory pool; a first address table mapping the first memory expansion pool to the first memory pool based on a size of the first memory expansion pool or a size of the first memory pool; and a second address table mapping the second memory expansion pool to the second memory pool based on a size of the second memory expansion pool or a size of the second memory pool.

公开(公告)号：US20230318921A1

公开(公告)日：2023-10-05

申请号：US17657977

申请日：2022-04-05

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Dinesh D. Gaitonde

IPC: H04L41/0893 ,  H04L49/109 ,  H04J3/02

CPC classification number: H04L41/0893 ,  H04J3/02 ,  H04L49/109

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

公开(公告)号：US11777489B1

公开(公告)日：2023-10-03

申请号：US17747387

申请日：2022-05-18

Applicant: Xilinx, Inc.

Inventor： Hari Bilash Dubey ,  Milind Goel ,  Venkata Siva Satya Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama Subrahmanyam Lanka

IPC: H03K17/22 ,  H03K17/10 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/223 ,  H03K17/102 ,  H03K19/0013 ,  H03K19/00315

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.

公开(公告)号：US20230308384A1

公开(公告)日：2023-09-28

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Jaideep DASTIDAR ,  Jeffrey CUPPETT ,  Sagheer AHMAD

IPC: H04L49/109 ,  H04L45/24 ,  H04L45/74

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US20230305949A1

公开(公告)日：2023-09-28

申请号：US17656236

申请日：2022-03-24

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F11/36 ,  G06F8/30

CPC classification number: G06F11/3688 ,  G06F8/311

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

公开(公告)号：US11769710B2

公开(公告)日：2023-09-26

申请号：US16833034

申请日：2020-03-27

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Ken Chang ,  Mayank Raj ,  Chuan Xie ,  Yohan Frans

IPC: H01L23/473 ,  H01L25/16 ,  H01L23/367 ,  H01L23/40

CPC classification number: H01L23/473 ,  H01L23/3675 ,  H01L25/167 ,  H01L2023/4062

Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

公开(公告)号：US20230299802A1

公开(公告)日：2023-09-21

申请号：US17698871

申请日：2022-03-18

Applicant: XILINX, INC.

Inventor： Hari Bilash DUBEY ,  Lanka Sasi Rama SUBRAHMANYAM

IPC: H04B1/18 ,  H04B1/16

CPC classification number: H04B1/18 ,  H04B1/1676

Abstract: Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.

公开(公告)号：US11762762B1

公开(公告)日：2023-09-19

申请号：US17656236

申请日：2022-03-24

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F11/36 ,  G06F8/30

CPC classification number: G06F11/3688 ,  G06F8/311

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

公开(公告)号：US20230289500A1

公开(公告)日：2023-09-14

申请号：US17692602

申请日：2022-03-11

Applicant: Xilinx, Inc.

Inventor： Anindita Patra ,  Ali Behboodian ,  Michael Gill

IPC: G06F30/31

CPC classification number: G06F30/31

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.