公开(公告)号：US20100182068A1

公开(公告)日：2010-07-22

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G06G7/12

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

公开(公告)号：US07426000B2

公开(公告)日：2008-09-16

申请号：US11403292

申请日：2006-04-13

Applicant: Sung-Jin Kim ,  Young-Wook Lee ,  Keun-Kyu Song ,  Mun-Pyo Hong

Inventor： Sung-Jin Kim ,  Young-Wook Lee ,  Keun-Kyu Song ,  Mun-Pyo Hong

IPC: G02F1/136

CPC classification number: H01L29/78696 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/42392

Abstract: A transistor includes a wire formed on a substrate, the wire comprising a semiconductor core, a first cover enclosing a portion of the semiconductor core, and a second cover enclosing the first cover, a first electrode formed on the second cover of the wire, an insulating layer formed on the first electrode and having contact holes exposing portions the semiconductor core, and a second electrode and a third electrode connected to the wire through the contact holes.

Abstract translation: 晶体管包括形成在基板上的导线，所述导线包括半导体芯，封装半导体芯的一部分的第一盖和封闭第一盖的第二盖，形成在导线的第二盖上的第一电极， 绝缘层，其形成在所述第一电极上，并且具有暴露所述半导体芯的部分的接触孔，以及通过所述接触孔连接到所述电线的第二电极和第三电极。

公开(公告)号：US07172913B2

公开(公告)日：2007-02-06

申请号：US11082967

申请日：2005-03-18

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US08723179B2

公开(公告)日：2014-05-13

申请号：US12957743

申请日：2010-12-01

Applicant: Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20120211822A1

公开(公告)日：2012-08-23

申请号：US13462082

申请日：2012-05-02

Applicant: Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

Inventor： Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

IPC: H01L29/792

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Abstract translation: 一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽 在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出 衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

公开(公告)号：US08174020B2

公开(公告)日：2012-05-08

申请号：US12556277

申请日：2009-09-09

Applicant: Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L27/14

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08144280B2

公开(公告)日：2012-03-27

申请号：US12152619

申请日：2008-05-14

Applicant: Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC: G02F1/136 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/136209 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.

Abstract translation: 提供了一种液晶显示器，用于防止光泄漏，同时提高了开口率和减少了数据线的负载。 液晶显示器包括形成在绝缘基板上并且彼此分开的栅极线和存储电极线，与栅极线相交的第一数据线和第二数据线，由栅极线和第一栅极线限定的第一像素电极 数据线和由栅极线和第二数据线限定并与第一像素电极相邻的第二像素电极。 此外，包括第一像素电极和第二像素电极之间的阻挡电极，其中第一数据线的至少一部分设置在第一像素电极下方，并且阻挡电极的至少一部分设置在第二像素电极下方 并且除了第一条数据线之外。

公开(公告)号：US20110227063A1

公开(公告)日：2011-09-22

申请号：US13046130

申请日：2011-03-11

Applicant: Pil-Sang YUN ,  Young-Wook LEE ,  Woo-Geun LEE

Inventor： Pil-Sang YUN ,  Young-Wook LEE ,  Woo-Geun LEE

IPC: H01L29/786 ,  H01L33/00

CPC classification number: H01L21/467 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided is an oxide thin-film transistor (TFT) substrate that may enhance the display quality of a display device and a method of fabricating the same via a simple process. The oxide TFT substrate includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.

Abstract translation: 提供了可以通过简单的处理来提高显示装置的显示质量的氧化物薄膜晶体管（TFT）基板及其制造方法。 氧化物TFT基板包括：基板，栅极线，数据线，氧化物TFT和像素电极。 氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。 第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

公开(公告)号：US20100032664A1

公开(公告)日：2010-02-11

申请号：US12502653

申请日：2009-07-14

Applicant: Young-Wook LEE ,  Hong-Suk YOO ,  Jean-Ho SONG ,  Jae-Hyoung YOUN ,  Jong-In KIM

Inventor： Young-Wook LEE ,  Hong-Suk YOO ,  Jean-Ho SONG ,  Jae-Hyoung YOUN ,  Jong-In KIM

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1225

Abstract: An oxide semiconductor thin film transistor substrate includes a gate line and a gate electrode disposed on an insulating substrate, an oxide semiconductor pattern disposed adjacent to the gate electrode, a data line electrically insulated from the gate line, the data line and the gate line defining a display region, a first opening exposing a surface of the data line, a second opening exposing a surface of the oxide semiconductor pattern, and a drain electrode disposed on the first opening and a drain electrode pad, the drain electrode extending from the first opening to the second opening and electrically connecting the drain electrode pad and the oxide semiconductor pattern.

Abstract translation: 氧化物半导体薄膜晶体管基板包括栅极线和设置在绝缘基板上的栅电极，邻近栅电极设置的氧化物半导体图案，与栅极线电绝缘的数据线，数据线和限定线 显示区域，暴露数据线的表面的第一开口，暴露氧化物半导体图案的表面的第二开口和设置在第一开口上的漏电极和漏电极焊盘，漏电极从第一开口延伸 到第二开口并电连接漏电极焊盘和氧化物半导体图案。

公开(公告)号：US20090309099A1

公开(公告)日：2009-12-17

申请号：US12268725

申请日：2008-11-11

Applicant: Jong-In Kim ,  Jang-Soo Kim ,  Young-Wook Lee

Inventor： Jong-In Kim ,  Jang-Soo Kim ,  Young-Wook Lee

IPC: H01L27/08 ,  H01L21/77

CPC classification number: H01L27/12 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: The present invention relates to a display device and a manufacturing method thereof. The display device includes a substrate, a first conductor disposed on the substrate, a first insulating layer disposed on the first conductor, a second insulating layer disposed on the first insulating layer, a semiconductor disposed on the second insulating layer, and a second conductor disposed on the semiconductor. A thickness of the first insulating layer is greater than a thickness of the first conductor, and the first insulating layer includes a first opening exposing the first conductor.

Abstract translation: 显示装置及其制造方法技术领域本发明涉及显示装置及其制造方法。 显示装置包括基板，设置在基板上的第一导体，设置在第一导体上的第一绝缘层，设置在第一绝缘层上的第二绝缘层，设置在第二绝缘层上的半导体和设置在第二绝缘层上的第二导体 在半导体上。 第一绝缘层的厚度大于第一导体的厚度，第一绝缘层包括暴露第一导体的第一开口。