公开(公告)号：US06828627B2

公开(公告)日：2004-12-07

申请号：US10742952

申请日：2003-12-23

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US06819592B2

公开(公告)日：2004-11-16

申请号：US10108574

申请日：2002-03-29

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US06703669B1

公开(公告)日：2004-03-09

申请号：US09714228

申请日：2000-11-17

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US20190206889A1

公开(公告)日：2019-07-04

申请号：US15858509

申请日：2017-12-29

申请人： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

发明人： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC分类号： H01L27/11573 ,  H01L27/11556 ,  H01L23/528 ,  H01L29/36 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/11526 ,  H01L29/66 ,  H01L29/16 ,  H01L23/532 ,  G11C16/08 ,  G11C16/24

摘要： Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US09251907B2

公开(公告)日：2016-02-02

申请号：US13438331

申请日：2012-04-03

申请人： Akira Goda ,  Yijie Zhao ,  Krishna Parat

发明人： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.

摘要翻译： 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。

公开(公告)号：US08921891B2

公开(公告)日：2014-12-30

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L21/336

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08742481B2

公开(公告)日：2014-06-03

申请号：US13211033

申请日：2011-08-16

申请人： Paolo Tessariol ,  Aurelio Giancarlo Mauri ,  Akira Goda ,  Yijie Zhao

发明人： Paolo Tessariol ,  Aurelio Giancarlo Mauri ,  Akira Goda ,  Yijie Zhao

IPC分类号： H01L27/108

CPC分类号： H01L29/1054 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.

摘要翻译： 示出了诸如存储器件，存储器单元串和电子系统的装置以及形成这种装置的方法。 一种这样的装置包括在一个或多个端部处具有比在中间部分中具有较低的少数载流子寿命的沟道区域。 还公开了其它装置和方法。

公开(公告)号：US08705290B2

公开(公告)日：2014-04-22

申请号：US13621052

申请日：2012-09-15

申请人： Prashant S. Damle ,  Krishna K. Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

发明人： Prashant S. Damle ,  Krishna K. Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.

摘要翻译： 一些实施例包括具有模块和存储器单元的方法和装置。 该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

公开(公告)号：US20140054666A1

公开(公告)日：2014-02-27

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L29/788

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08493790B2

公开(公告)日：2013-07-23

申请号：US13308020

申请日：2011-11-30

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts.

摘要翻译： 公开了编程，读取和擦除存储器单元的方法。 在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏 零伏。