公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

公开(公告)号：US07994837B1

公开(公告)日：2011-08-09

申请号：US12537634

申请日：2009-08-07

申请人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang

发明人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang

IPC分类号： H03H11/16

CPC分类号： H03H11/22

摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

摘要翻译： 相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路 负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。 相位内插器电路可以包括三个差分对的晶体管。 具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。 相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

公开(公告)号：US07639993B1

公开(公告)日：2009-12-29

申请号：US11295391

申请日：2005-12-05

申请人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

发明人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H04B1/04

CPC分类号： H04L7/033

摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.

摘要翻译： 集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。 在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

公开(公告)号：US07276936B1

公开(公告)日：2007-10-02

申请号：US11239702

申请日：2005-09-29

申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

IPC分类号： H03K19/00

CPC分类号： H03K19/1774 ,  H03K19/17744

摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

摘要翻译： 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。

公开(公告)号：US08222967B1

公开(公告)日：2012-07-17

申请号：US12644128

申请日：2009-12-22

申请人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

发明人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

IPC分类号： H03H7/30 ,  H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/405 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45686 ,  H03F2203/7236 ,  H03H11/1213 ,  H03H11/48

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

摘要翻译： 集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。 每个NMOS级可包括折叠的有源电感电路。 每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化 。 例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。 在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

公开(公告)号：US20120063556A1

公开(公告)日：2012-03-15

申请号：US12881160

申请日：2010-09-13

申请人： Tim Tri Hoang

发明人： Tim Tri Hoang

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/183

摘要： A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols.

摘要翻译： 电路包括相位检测电路，相位调整电路和采样电路。 相位检测电路将第一周期信号的相位与第二周期信号的相位进行比较，以产生控制信号。 相位调整电路使得第二周期信号的相位和第三周期信号的相位根据控制信号的变化而变化。 采样器电路对数据信号进行采样，以响应于第三周期信号产生采样数据信号。 电路改变第三周期信号的频率以对应于基于至少三个数据传输协议的至少三个不同数据速率之间的数据信号的数据速率的变化。

公开(公告)号：US07602255B1

公开(公告)日：2009-10-13

申请号：US11861144

申请日：2007-09-25

申请人： Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

发明人： Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

IPC分类号： H03L7/00

CPC分类号： H03L7/0895 ,  H03L7/0812

摘要： A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

摘要翻译： 在集成电路上的反馈回路（例如锁相环）具有检测器，电荷泵和环路滤波器。 电荷泵响应于集成电路的过程中的变化来调节其输出电流，以减少环路带宽的变化。 电荷泵还响应于环路滤波器中的电阻器的电阻的变化来调整其输出电流，以减少环路带宽的变化。 电荷泵还可以响应于集成电路的温度变化来调节其输出电流，以减少环路带宽的变化。 集成电路上的延迟锁定环路具有相位检测器和电荷泵。 电荷泵响应于集成电路的温度和过程的变化来调整其输出电流，以减少环路带宽的变化。

公开(公告)号：US08816745B1

公开(公告)日：2014-08-26

申请号：US13316361

申请日：2011-12-09

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03L5/00

CPC分类号： H04L25/03878 ,  H03K19/018507

摘要： An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

摘要翻译： 提供了包括基于电感器和非电感器的均衡器级的均衡器电路。 在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。 在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。 在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

公开(公告)号：US08705605B1

公开(公告)日：2014-04-22

申请号：US13288701

申请日：2011-11-03

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L1/243 ,  H04B17/14 ,  H04L25/03878 ,  H04W52/0274 ,  Y02D70/00

摘要： Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

摘要翻译： 提供了集成电路（IC）中串行回送测试的设备和方法。 为了实现环回测试，IC的接收机的均衡器级掉电。 此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。 这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

公开(公告)号：US08188774B1

公开(公告)日：2012-05-29

申请号：US12833718

申请日：2010-07-09

申请人： Gopi Krishnamurthy ,  Binh Ton ,  Ning Xue ,  Tim Tri Hoang ,  Michael Menghui Zheng ,  Weiqi Ding

发明人： Gopi Krishnamurthy ,  Binh Ton ,  Ning Xue ,  Tim Tri Hoang ,  Michael Menghui Zheng ,  Weiqi Ding

IPC分类号： H03L7/00

CPC分类号： H03K19/1774

摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

摘要翻译： 一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。 收发器通道的偏移校准由物理介质连接电路执行。 传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。 随后，当集成电路的核心部件变得可操作时，该接口被激活。 另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。 另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。 还公开了其它实施例，方面和特征。